I've been designing a one-shot as part of my EE senior project and am unable to get the 'Reset' to toggle the output to 0.
I used the RTL_viewer in Quartus and the design does match my code: The DFF output (Q) is fed into 2 inverters then into the DFF Reset.
My understanding is that the two inverters should act as buffers. The DFF output should be 0 until the next clock edge is reached. I'm not sure if something is wrong with my design or if this is a timing error. I tried playing around with the clock speed and the buffer delay, but neither produced the correct results.
module oneShot(Clk, Q, Q_bar);
input Clk;
output Q, Q_bar;
logic X, Reset /* synthesis keep */;
logic D = 1'b1;
parameter propogation_delay = 30ns;
not #(propogation_delay) (X, Q);
not #(propogation_delay) (Reset, X);
//instantiation of flip flop
//DFF (Clk, Reset, D, Q);
DFF1 unit0 (Clk, Reset, D, Q);
assign Q_bar = ~ Q;
endmodule
module DFF1 (Clk, Reset, D, Q);
input Clk, Reset, D;
output logic Q;
always_ff #(posedge Clk)
begin
if(Reset == 1'b1)
Q <= 0;
else
Q <= D;
end
endmodule
module oneShot_tb;
logic Clk, Q, Q_bar, Reset;
oneShot DUT (Clk, Q, Q_bar);
always begin
Clk = 0;
#10;
Clk = 1'b1;
#10;
end
initial begin
#300;
$stop;
end
Related
I'm trying to implement this debouncer circuit in Verilog. This is the code I got, and I believe it should work, but it doesn't. The problem is that the button_debounce signal is always 0.
module divider(clk, reset, divded_clock_out);
input clk;
input reset;
output reg divded_clock_out;
reg [19:0]counter;
always #(posedge clk or negedge reset)
begin
if(!reset)
counter <= 0;
else
begin
if (counter == 999999)
counter <= 0;
else
counter <= counter + 1;
if (counter < 499999)
divded_clock_out <= 0;
else
divded_clock_out <= 1;
end
end
endmodule
module dff(clk, D, Q, reset);
input clk;
input reset;
input D;
output reg Q;
always # (posedge clk or posedge reset)
begin
if(reset)
Q <= 1'b0;
else
Q <= D;
end
endmodule
module debounce(clk, button, button_debounce, reset);
input clk;
input reset;
input button;
output button_debounce;
wire [2:0]reg_wire;
dff reg1(clk, button, reg_wire[0], reset);
dff reg2(clk, reg_wire[0], reg_wire[1], reset);
dff reg3(clk, reg_wire[1], reg_wire[2], reset);
assign button_debounce = reg_wire[0] & reg_wire[1] & reg_wire[2];
endmodule
module debouncer_tb();
reg clk;
reg reset;
reg button;
wire divded_clock_out;
wire button_debounce;
initial begin
clk = 0;
reset = 0;
button = 0;
#10;
reset = 1;
button = 1;
end
always #10 clk=~clk;
divider uut(clk, reset, divded_clock_out);
debounce uut2(divded_clock_out, button, button_debounce);
endmodule
The divider works as expected, and I believe it's only a problem with the debouncer module. For the simulation testbench, the output of the divider is correct and the output of the debouncer is always 0, and it should be 1 when the button input changes to 1.
When I run a simulation, I get the following compile warning:
debounce uut2(divded_clock_out, button, button_debounce);
|
xmelab: *W,CUVWSI : 1 input port was not connected:
xmelab: reset
The debounce module has 4 ports, but you only connected 3 of them. Check your log files to see if you have a similar message.
Also, when I run the simulation, I see button_debounce as X (unknown), not 0.
When I change:
debounce uut2(divded_clock_out, button, button_debounce);
to:
debounce uut2(divded_clock_out, button, button_debounce, ~reset);
I see button_debounce go to 1, as desired. I added reset to the connection list. Note that I inverted the reset signal because your dff modules use an active-high reset, whereas the divider uses an active-low reset.
However, using connection-by-order, as shown above, is error prone. It is better to use connection-by-name:
debounce uut2 (
.clk (divded_clock_out),
.button (button),
.button_debounce (button_debounce),
.reset (~reset)
);
I have written the testbench code and design code for Master-slave JK flip flop, but output isn't coming.
Please point out the error.
Test bench.sv
module JK_ff_tb;
reg clk;
reg reset;
reg j,k;
wire q;
wire qb;
jk_flip_flop_master_slave jkflipflop( .clk(clk), .reset(reset), .j(j), .k(k), .q(q), .q_bar(qb) );
initial begin
$dumpfile("dump.vcd"); $dumpvars;
$monitor(clk,j,k,q,qb,reset);
j = 1'b0;
k = 1'b0;
reset = 1;
clk=1;
#10
reset=0;
j=1'b1;
k=1'b0;
#100
reset=0;
j=1'b0;
k=1'b1;
#100
reset=0;
j=1'b1;
k=1'b1;
#100
reset=0;
j=1'b0;
k=1'b0;
#100
reset=1;
j=1'b1;
k=1'b0;
end
always #25 clk <= ~clk;
endmodule
Design.sv
module jk_flip_flop_master_slave(j,k,clk,reset,q,q_bar);
input j,k,clk,reset;
output q,q_bar;
reg q,q_bar; // Active low reset signal.
wire MQ; // The master's Q output.
wire MQn; // The master's Qn output.
wire Cn; // The clock input to the slave shall be the complement of the master's.
wire J1;
wire K1;
wire J2; // The actual input to the first SR latch (S).
wire K2; // The actual input to the first SR latch (R).
assign J2 = !reset ? 0 : J1; // Upon reset force J2 = 0
assign K2 = !reset ? 1 : K1; // Upon reset force K2 = 1
and(J1, j, q_bar);
and(K1, k, q);
not(Cn, clk);
sr_latch_gated master(MQ, MQn, clk, J2, K2);
sr_latch_gated slave(q, q_bar, Cn, MQ, MQn);
endmodule // jk_flip_flop_master_slave
Sr_Latched flip flop module
module sr_latch_gated(Q, Qn, G, S, R);
output Q;
output Qn;
input G;
input S;
input R;
wire S1;
wire R1;
and(S1, G, S);
and(R1, G, R);
nor(Qn, S1, Q);
nor(Q, R1, Qn);
endmodule // sr_latch_gated
I have coded the entire thing in EDA-playground.
The diagram generated was really abrupt as well.
If there is another logic that can be implemented easily, do tell.
I get compile errors on 2 different simulators. You should not declare q and q_bar as reg in the jk_flip_flop_master_slave module. You should delete this line:
reg q,q_bar; // Active low reset signal.
Then it compiles and simulates for me. I see this output:
100xx1
110xx0
010010
110010
010010
110010
101010
001010
101010
001010
...
module rff_try_1(q,inp,clk);
input clk,inp;
output q;
reg q;
DFF dff0(q,inp,clk);
endmodule
module DFF(q,inp,clk);
input inp,clk;
output q;
reg q;
always # (posedge clk)begin
if(clk)begin
q=inp;
end
end
endmodule
here I'm using two modules but output is not coming
I'm trying to make two bit right shift register but 1st i have to make one single bit register but even this is not working
There are several mistakes in the code.
1) The line if(clk)begin and relevant end should be removed, posedge clk already describes trigger condition of the flip-flop.
2) A non-blocking assignment (<=) is required for the sequential logic.
The always block should be as follows:
always # (posedge clk) begin
q <= inp;
end
3) Some simulators don't complain, but signal q should be wire in module rff_try_1.
wire q;
Simulation
I simulated the code (after the modifications) on EDA Playground with the testbench below. Used Icarus Verilog 0.9.7 as simulator.
module tb();
reg clk = 1;
always clk = #5 ~clk;
reg inp;
wire q;
rff_try_1 dut(q, inp, clk);
initial begin
inp = 0;
#12;
inp = 1;
#27;
inp = 0;
#24;
inp = 1;
end
initial begin
$dumpfile("dump.vcd"); $dumpvars;
#200;
$finish;
end
endmodule
The signal q is as expected as seen on the waveform.
I am a beginner in designing circuit using verilog in modelsim. I use a sample code and a tutorial to learn how modelsim works. The code and the testbench are compiled without any problem and even testbench is simulated without any error but the input and output signals are not shown in object windows and they are not under instance menu. please describe for me how can I find them and simulate the waveforms.
here is my code and the test bench.
the definition of a D flipflop
// module D_FF with synchronous reset
module D_FF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
// Lots of new constructs. Ignore the functionality of the
// constructs.
// Concentrate on how the design block is built in a top-down fashion.
always #(negedge clk or posedge reset)
if (reset)
q <= 1'b0;
else
q <= d;
endmodule
the definition of a T flipflop from D
module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q);
endmodule
counter codes:
module rcc4(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module T_FF are created.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule
testbench code:
module stimulus();
reg clk;
reg reset;
wire[3:0] q;
// instantiate the design block
rcc4 r1(q, clk, reset);
// Control the clk signal that drives the design block. Cycle time = 10
initial
clk = 1'b0; //set clk to 0
always
#5 clk = ~clk; //toggle clk every 5 time units
// Control the reset signal that drives the design block
// reset is asserted from 0 to 20 and from 200 to 220.
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish; //terminate the simulation
end
// Monitor the outputs
initial
$monitor($time, " Output q = %d", q);
endmodule
I am using modelsim 10.1c on Windows 10.
The following picture is from my project and it shows my object and instance window.
The switch -voptargs=+acc will solve your issue.
vsim -voptargs=+acc modulename
I was going through a document from Microsemi website (Actel HDL Code) and I found a few implementations of flip-flop (Synchronous, Asynchronous etc.).In all the cases the author has modelled the flip-flops with blocking statements.
I want to know are these implementations correct, because I have always used non blocking to model sequential logic? Am I missing something or is it just a way to model only flip flop and not a sequential circuit in general?
// Rising Edge Flip-Flop with Asynchronous Reset
module dff_async_rst (data, clk, reset, q);
input data, clk, reset;
output q;
reg q;
always #(posedge clk or negedge reset)
if (~reset)
q = 1'b0;
else
q = data;
endmodule
//Rising Edge Flip-Flop with Synchronous Reset
module dff_sync_rst (data, clk, reset, q);
input data, clk, reset;
output q;
reg q;
always # (posedge clk)
if (~reset)
q = 1'b0;
else
q = data;
endmodule
NOTE : Blocking assignments used in always block to get a sequential logic
Flip-flops should be modelled with non-blocking (<=) as you previously thought.
If your using any version of verilog after 1995 then your port declarations can be tidied up a little. NB I add begin ends for clarity and _n to designate active low signals.
Rising Edge Flip-Flop with Asynchronous Reset
module dff_async_rst (
input data,
input clk,
input reset_n,
output reg q //SystemVerilog logic is preferred over reg
);
always #(posedge clk or negedge reset_n) begin
if (~reset_n) begin
q <= 1'b0;
end
else begin
q <= data;
end
end
endmodule
Rising Edge Flip-Flop with Synchronous Reset
module dff_sync_rst(
input data,
input clk,
input reset_n,
output reg q //SystemVerilog logic is preferred over reg
);
always #(posedge clk) begin
if (~reset_n) begin
q <= 1'b0;
end
else begin
q <= data;
end
end
endmodule