internally generating resets verilog 2005 - verilog

Question

wanted to implement PWM sequence using top-level verilog 2005 module:
module PWM_ENHANCER (
input clk,
input rst,
input sent,
//input
input [7:0] BUF, //BUFFER - The PWM reads from it only when 'sent' signal is received, and the current run is done.
//output
output reg PWM_WAIT,
output reg PWM_OUT
);
reg [7:0] SAMPLE;
reg [7:0] counter;
reg WORK;
always#(posedge clk or negedge rst)
begin
if( !rst )
begin
WORK <= 1'b0; //When receiving a reset, everything zeroes.
counter <= 8'b0;
PWM_WAIT <= 1'b1;
SAMPLE <= 8'b0;
PWM_OUT <= 1'b0;
end
else if (sent == 1 && WORK == 0)
begin //If the pwm was OFF, and i received sign from the array, i start running PWM.
SAMPLE <= BUF;
WORK <= 1'b1;
PWM_WAIT <= 1'b0;
end
else if(WORK == 1)
begin //The running block - sending '0' and '1' as needed.
if ( (counter <= SAMPLE) && (SAMPLE != 0) )
begin
PWM_OUT <= 1'b1;
counter = counter + 1'b1;
end
else if ( counter > SAMPLE )
begin
if ( counter == 8'b11111111 )
begin
counter <= 8'b0;
WORK <= 1'b0;
end
else
begin
counter = counter + 1'b1;
PWM_OUT <= 1'b0;
end
end;
if(counter == 200)
begin // 50 cycles before the end, PWM sends acknowledge for the array to send the next sample.
PWM_WAIT <= 1'b1;
end
end
else
begin
; // if NOT receiving 'sent' from the array - the PWM does nothing.
end
end
endmodule
received error when compiling:
"Internally generated reset in top design unit 'PWM_ENHANCER' is not allowed."
How can i have a reset included in the #always statement?

Answer 1

Two possibility (both synthesis related):
Your synthesizer needs additional hand-holding for the asynchronous reset
if(!rst) begin
WORK <= 1'b0;
counter <= 8'b0;
PWM_WAIT <= 1'b1;
SAMPLE <= 8'b0;
PWM_OUT <= 1'b0;
end
else begin
// other logic in here
end
Your standard cell library lacks flops with asynchronous reset/preset. FPGA's tend to have a limited number of flops with asynchronous reset/preset. Some FPGA do not have any. If this is the case the simplest thing that can be done is change the for asynchronous reset to synchronous reset by changing the top of your always block to always#(posedge clk) (omitting the or negedge rst).
If you are on FPGA, then you may want to add an initial block to initialize the defaults of the registers.