I am trying to implement RSA on and virtex 5 FPGA using verilog. Xilinx ISE logs aren't very descriptive. I'm using a CORDIC 4.0 IP core and a Random number generator. I've been working on this for the past week and I can't seem to get it straight.
MAIN FILE
`include "GARO.v"
module RSA_Encryption(RST_N,CLOCK,CTEXTPUB,RANDP,RANDQ,RANDE,PRIME_CHECK,PRIME_CHECKED,MESSAGE,RECEIVED);
//******************************************************
//Declarations
//******************************************************
reg RST_N;
input wire CLOCK;
input wire [31:0] PRIME_CHECKED;
output wire [31:0] PRIME_CHECK;
input wire [31:0] RANDP;
input wire [31:0] RANDQ;
input wire [31:0] RANDE;
integer randp;
integer randq;
integer phi;
integer e;
integer d;
integer mod = 0;
integer i = 0;
input wire [31:0] MESSAGE;
input wire [31:0] RECEIVED;
integer message;
integer received;
integer sqroot;
output wire [31:0] CTEXTPUB;
RST_N = 1;
d = 1;
//******************************************************
//******************************************************
//Calling random number generator module to get random numbers via wires: RANDP, RANDQ and RANDE
//******************************************************
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDP);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDQ);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDE);
//******************************************************
//******************************************************
//Assigning random numbers from respective wires to integer variables randp, randq and e
//******************************************************
e = RANDE;
randp = RANDP;
randq = RANDQ;
//******************************************************
//******************************************************
//Check whether randp is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randp);
for(i = 0 ; i <= sqroot ; i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randp = RANDP;
end while(1);
//******************************************************
//******************************************************
//Check whether randq is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randq);
for(int i = 0;i<=sqroot,i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randq = RANDQ;
end while(1);
//*******************************************************
//*******************************************************
//Computing 'phi'
//*******************************************************
phi = (randp-1)(randq-1);
//*******************************************************
//*******************************************************
//Selecting 'e'
//*******************************************************
do begin
e = RANDE;
end while(e < phi && e > 1);
//*******************************************************
//*******************************************************
//Checking if gcd(e,phi) is 1
//*******************************************************
do begin
rem = phi%e;
if(rem == 0 && e == 1)
begin
break;
end
else
begin
do begin
e = RANDE;
end while(e > phi && e > 1);
end
phi = e;
e = rem;
end while(1);
//***********************************************
//***********************************************
//Computing 'n'
//***********************************************
n = randp*randq;
//***********************************************
//***********************************************
//Calculating 'd'
//***********************************************
do begin
mod = (d*e)%phi;
d = d+1;
end while(mod != 1);
//***********************************************
//***********************************************
//Computing Ciphertext using public key i.e (n,e)
//***********************************************
message = MESSAGE;
do begin
message = message*message;
e--;
end while(e != 0);
CTEXTPUB = message%n;
//***********************************************
//***********************************************
//Decrypting ciphertext using private key i.e (n,d)
//***********************************************
received = RECEIVED;
do begin
received = received*received;
d = d-1;
end while (d != 0);
received = received%n;
//************************************************
endmodule
RANDOM NUMBER GENERATOR
module fibonacci_lfsr_nbit
#(parameter BITS = 32)
(
input clk,
input rst_n,
output reg [31:0] data
);
reg [31:0] data_next;
always_comb begin
data_next = data;
repeat(BITS) begin
data_next = {(data_next[31]^data_next[1]), data_next[31:1]};
end
end
always_ff #(posedge clk or negedge rst_n) begin
if(!rst_n)
data <= 32'h1f1f;
else
data <= data_next;
end
end
endmodule
HERE'S THE IP CORE API
`timescale 1 ns/1 ps
module Square_Root_CORDIC_Core_IP (
clk, x_out, x_in
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [31 : 0] x_out;
input [31 : 0] x_in;
LOGS
Started : "Behavioral Check Syntax".
Determining files marked for global include in the design...
Running vlogcomp...
Command Line: vlogcomp -work isim_temp -intstyle ise -prj G:/Xilinx_Projects/first_project/RSA/RSA_Encryption_stx_beh.prj
Determining compilation order of HDL files
Analyzing Verilog file "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" into library isim_temp
ERROR:HDLCompiler:806 - "GARO.v" Line 11: Syntax error near "begin".
ERROR:HDLCompiler:525 - "GARO.v" Line 14: Inconsistent dimension in declaration
ERROR:HDLCompiler:806 - "GARO.v" Line 14: Syntax error near "}".
ERROR:HDLCompiler:598 - "GARO.v" Line 1: Module <fibonacci_lfsr_nbit> ignored due to previous errors.
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 32: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 57: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 70: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 71: Syntax error near "+".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 75: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 78: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 92: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 93: Syntax error near "i".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 149: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 154: Syntax error near "begin".
ERROR:HDLCompiler:53 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: <RST_N> is not a port.
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 230: d is an unknown type
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 232: received is an unknown type
ERROR:HDLCompiler:598 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: Module <RSA_Encryption> ignored due to previous errors.
Verilog file G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v ignored due to errors
Process "Behavioral Check Syntax" failed
Process "Behavioral Check Syntax" failed
There are a lot of things wrong here.
The most important problem, though, is that you are trying to write Verilog code as if it's a procedural programming language. This won't work; Verilog is a hardware description language. You cannot use constructs like for and while loops to implement iteration in hardware; these operations must be implemented as clocked logic.
Get a good textbook on FPGA design and work through it. You have a lot to learn.
If this is coursework: contact your professor or a teaching assistant now. You are not going to make your deadline.
Related
the function is: when h posedge come, start count clk, if count to 105, r set 0, if count to 517, r set to 1; if count over 600,do nothing;
h is a periodic singal;
module make_counter(h, clk, P);
input wire h;
input wire clk;
output wire P;
reg r=1'b1;
reg[9:0] n=0;
always #(negedge clk)
always #(posedge h)
begin
n=0;
end
begin
if(n<600)
n=n+1'b1;
if(n==106)
r<=1'b0;
else if(n==517)
r<=1'b1;
else
;
end
assign P=r;
endmodule
Error (10170): Verilog HDL syntax error at main.v(115) near text "always"; expecting ";"
Error (10170): Verilog HDL syntax error at main.v(119) near text "begin"; expecting "endmodule"
zhe image is what i want. when flag1 start set n=0, and count clk;
when count to flag2, set P=0; when count to red arrow, set P=1;
Buddy you have some sort of bad code,
Don't use always block inside always block
Make variable name meaning full i.e. cnt instead of n
Use reset, and avoid value assignment at declaration
module make_counter(h, clk, P);
input wire h;
input wire clk;
output wire P;
wire r;
reg[9:0] n=0;
always # (posedge clk or posedge h)
begin
if(h & (n < 10'd600)) begin
n <= n + 1'd1;
end else begin
n <= n;
end
end
assign r = (n == 10'd105) ? 1'b0 : ( (n == 10'd517) ? 1'b1 : 1'bx );
assign P = r;
endmodule
You have not mentioned that, what should be the value of r if n is in between 0 to 104 and 106 to 516 and > 517?
I assumed it ll be anything.
Check it and say it works for you
So I am doing a pre-lab assignment for my digital systems course in which we are supposed to test certain components and ultimately create a counter from them. The issue I'm having is that the code the professor gave us won't compile. This specific test fixture (ISE Design Suite 14.7) is describing a shift register.
module kg4014TB;
// Inputs
reg Clock;
reg Ser_In;
reg [7:0] P;
reg ParLoadCTRL;
// Outputs
wire Q7;
wire Q6;
wire Q5;
// Instantiate the Unit Under Test (UUT)
kg4014 uut (
.Clock(Clock),
.Ser_In(Ser_In),
.P(P),
.ParLoadCTRL(ParLoadCTRL),
.Q7(Q7),
.Q6(Q6),
.Q5(Q5)
);
initial begin
// Initialize Inputs
Clock = 0;
Ser_In = 0;
P = 8'b11011111
#100;
ParLoadCTRL = 1;
// Wait 100 ns for global reset to finish
#700;
ParLoadCTRL = 0; //shift mode
#15000;
// Add stimulus here
end
always begin
#500 Clock = ~Clock;
end
endmodule
Here's the error message(s):
ERROR:HDLCompiler:806 - "C:/Xilinx/14.7/.v" Line 54: Syntax error near "#".
ERROR:HDLCompiler:598 - "C:/Xilinx/14.7/.v" Line 25: Module <kg4014TB> ignored due to previous errors.
Although I don't think it makes any difference, I'll just point out that I deleted some of the file path and the file name for no apparent reason.
This line is missing a semicolon at the end:
P = 8'b11011111;
When i am trying to compile following verilog RTL cadence simulator is throwing a error as illegal operand for constant expression.
RTL is:
module selection_logic( data_out, data_in , valid_info);
input [(number_of_channel * per_channel_data) - 1 : 0] data_in;
input [number_of_channel - 1: 0] valid_info;
output reg [number_of_channel - 1 : 0] data_in;
integer i;
always #(*)
begin
for (i = 0; i < number_of_channel; i = i + 1)
begin
if (valid_info[i])
data_out[(per_channel_data*(i+1)) - 1: per_channel_data*i] = data_in[[(per_channel_data*(i+1)) - 1: per_channel_data*i]
else
data_out[(per_channel_data*(i+1)) - 1: per_channel_data*i] = {per_channel_data{1'b0};
end
end
endmodule
Array slicing using the arrayName[MSB:LSB] require MSB and LSB to be constants. Instead, use the arrayName[start_bit +: WIDTH], where WIDTH is a constant and start_bit can be a variable. Refer to
"Indexing vectors and arrays with +:" and "What is `+:` and `-:`?"
data_out[per_channel_data*i +: per_channel_data] = data_in[per_channel_data*i +: per_channel_data];
If stuck with with Verilog-1995, then add a second for-loop and assign each bit individually:
for(i=0; i<per_channel_data; i=i+1) begin
for(j=0; j<per_channel_data; j=j+1) begin
if (valid_info[i])
data_out[per_channel_data*i+j] = data_in[per_channel_data*i+j];
else
data_out[per_channel_data*i+j] = 1'b0;
end
end
module booth(num1,num2,prod);
input [22:0] num1,num2;
output [45:0] prod;
reg [22:0]num1_bar;
reg [46:0]sub_1;
reg [22:0]temp;
reg [22:0]result;
reg [1:0]sel;
reg [22:0]add;
reg [22:0]zeros;
assign temp = ~ num1;
assign num1_bar = temp + "00000000000000000000001";
assign sub_1 = {zeros[22:0], num2, "0"};
integer i;
always #* begin
for( i = 0; i < 22; i = i+1) begin
assign sel = sub_1[1:0];
if(sel == "10") begin
assign add = sub_1[46:24] + num1_bar;
assign sub_1 ={add[22],add,sub_1[23:1]};
end
elseif(sel == "01") begin
assign add = sub_1[46:24] + num1 ;
assign sub_1 ={add[22],add,sub_1[23:1]};
end
else begin
assign sub_1= {sub_1[46] ,sub_1[46:1]};
end
end
endmodule
I am trying to implement a floating point multiplier using carry look ahead adder and booth multiplier. After running the above code following errors has occurred only for the booth multiplier.
Please help me out.
ERRORS:
Summary Tue Apr 7 15:25:28 2015
Summary New
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 45. Syntax error near "begin".
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 49. Syntax error near "else".
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 54. Syntax error near "endmodule".
INFO ProjectMgmt:1845 - Analyzing Verilog file "D:/XILINX PROGRAM/bth/booth.v" into library work
You seem to have a confusion between VHDL and Verilog.
Vector constants in Verilog are in the form: Y'zXXXXXXX where Y is the number of bits of the vector, z is the base (b for binary, d for decimal, h for hexadecimal), and XXXX is the constante value in the specified base.
else if must separated
For example, the line:
if(sel == "10") begin
Must be rewritten as:
if(sel == 2'b10) begin
For large vectors, you can ommit the size specifier, and write the constant as this:
assign num1_bar = temp + 'b00000000000000000000001;
You are missing an end matching the begin of the always block.
(Once you have fixed that, you will see that there are other errors, too. See mcleod_ideafix's answer.)
I'm trying to write a Verilog module that multiplies two 4bit inputs, without using * operator, but I get some errors:
module multiplier(
output[7:0] prod,
input[3:0] a,
input[3:0] b);
reg [7:0] result=8'h00;
always #(*)
begin
for(i=0;i<4;i=i+1)
begin
if((b&(1<<<i))!=0)
begin
result = result+(a<<<i);
end
end
end
assign prod = result;
endmodule
Errors:
[Synth 8-2715] syntax error near =
[Synth 8-2715] syntax error near =
[Synth 8-993] result is an unknown type
[Common 17-69] Command failed: Vivado Synthesis failed
What am I doing wrong?
EDIT:
I modified the code, now i get:
[Synth 8-1031] i is not declared
reg [7:0] result=16'h00;
Should be
reg [7:0] result=8'h00;
module multiplier(
output[7:0] prod,
input[3:0] a,
input[3:0] b);
reg [7:0] result;
reg[2:0] i;
always #(*)
begin
result=0;
for(i=0;i<4;i=i+1)
begin
if(b[i]==1'b1)
begin
result = result+(a<<i);
end
end
end
assign prod = result;
endmodule
For your code, if I had a = 15 and b = 15, the result would have been 72. You must assign a value for result in always block result=0;