Seems like ndk-build strips debug symbols when it copies .so from obj to lib folder. Is there a way to tell ndk-build not to strip the debug symbols?
In your Android.mk you could override cmd-strip to do what you want, e.g. nothing:
# Don't strip debug builds
ifeq ($(APP_OPTIM),debug)
cmd-strip :=
endif
Adding this to Application.mk solved it for me:
APP_STRIP_MODE := none
So, taking suggestions from #Michael and #gmetal:
ifeq ($(NDK_DEBUG),1)
APP_STRIP_MODE := none
endif
According to https://github.com/android/ndk/wiki/Changelog-r18-beta2
Use APP_STRIP_MODE in Application.mk of your NDK application
ifeq ($(NDK_DEBUG),1)
APP_STRIP_MODE := none
endif
OR LOCAL_STRIP_MODE in Android.mk of your NDK module
ifeq ($(NDK_DEBUG),1)
LOCAL_STRIP_MODE := none
endif
Related
all:
Why doesn't the following 3-line Makefile show any files at all;
even though I know there are files in $(SOURCE) directory.
There is no syntax errors.
Thank you in advance
SOURCE := src
CFILES := $(foreach, dir, $(SOURCE) , $(notdir $(wildcard $(dir)/*.c)))
all:
echo "$(CFILES)"
Phi Luu
First, you have a comma after the foreach which you don't want.
Second, you have to be very careful with whitespace in makefiles. Any trailing whitespace in a makefile, including in a function, is preserved as part of the word.
Rewrite this as:
CFILES := $(foreach dir,$(SOURCE),$(notdir $(wildcard $(dir)/*.c)))
Another option would be:
CFILES := $(wildcard $(addsuffix /*.c,$(SOURCE)))
I am pretty familiar with Makefiles and kernel modules, but recently I got a problem in my Makefile that doesn't make any sense -- on using wildcards.
To demonstrate this, I am compiling a hello world kernel module from scratch.
The directory structure is like this:
hello_mod/
|
--- hello.c
|
--- Makefile
Here is the actual makefile :
CFILES := $(wildcard hello.c*)
#CFILES := hello.c
OBJS := $(CFILES:.c=.o)
KSRC := /lib/modules/$(shell uname -r)/build
obj-m += hello_world.o
hello_world-y := $(OBJS)
all:
#echo $(CFILES)
$(MAKE) -C $(KSRC) M=$$PWD modules
clean:
$(MAKE) -C $(KSRC) M=$$PWD clean
.PHONY: clean
The problem is that even though the commented $(CFILES) and the uncommented $(CFILES) are exactly the same, the build fails on using the first $(CFILES) with the following error:
*** No rule to make target `/home/test/hello_mod/hello_world.c', needed by
/home/test/hello_mod/hello_world.o'. Stop.
If the commented $(CFILES) is used, it works perfectly.
If someone wants to test this out, I'm including the source for the hello world source which is hello.c :
#include <linux/kernel.h>
#include <linux/module.h>
static int mod_init()
{
printk("Hello\n");
return 0;
}
static void mod_exit()
{
printk("Bye world\n");
}
module_init(mod_init);
module_exit(mod_exit);
Does anyone know why it is behaving as such? And I need to use wildcards in the makefile. Any help will be appreciated.
There are two makes happening here. The first really only relies on the KSRC variable and the recursive make call. The second make only needs the CFILES, OBJS, obj-m, and hello_world-y variables, and doesn't make use of the all: target. So your debug is showing that CFILES is set correctly for the first Make, where it's not being used, and is not showing it in the second make, where it is.
You're wildcard expanding from a different directory, and not picking up the right files. Try this for CFILES:
CFILES := $(notdir $(wildcard $M/hello.c*))
SRCDIRS := subdir1 subdir2
CFILES := $(strip $(foreach dir,$(SRCDIRS),$(wildcard $(dir)/*.c)))
should probably be (see foreach example in documentation)
SRCDIRS := subdir1 subdir2
CFILES := $(foreach dir,$(SRCDIRS),$(wildcard $(dir)/*.c))
(no need to $(strip), .... or perhaps
CFILES := $(wildcard {subdir1,subdir2}/*.c)
Use remake, probably as remake -x, to debug such issues.
Trying to make makefile to turn all .c into execute files in directory.
For example:
am.c
2.c
s.c
into
am
2
s
programs.
Anything works,but it uses cc, but I want to use gcc compiler.
How can I do that?
SRC = $(wildcard *.c)
BIN = $(patsubst %.c,%,$(SRC))
all : $(BIN)
Add a line to the top saying
CC = gcc
I am trying to setup a Makefile with dependencies. The dependencies are specified in a variable.
MATH_VER=1.1
EXTERNAL_DEPS=MATH GC LOG
I want it to run a function that tries to figure out the location of each of the external libs based on whats available.
So I added a rule setversion,
all:setversion myexe
setversion:
$(foreach CHKLIB, $(EXTERNAL_DEPS), $(call checklib, $(CHKLIB)))
I have the function that does the checking
checklib = ifeq ($(wildcard $(ROOT)/$(var)/$(var)_VER),)
echo 'Bad dir'
$(var)_ROOT=$SOMEOTHERDIR
else
echo 'Good dir'
$(var)_ROOR=$(ROOT)/$(var)/$(var)_VER
endif
This dosent work - but I think it gives a good idea of what Im looking for. Can anyone point me to how this can be accomplished?
Thanks
Edit: I tested this out on my system and it seemed to do what you need.
define set_deps
ifeq ($(wildcard $(ROOT)/$(1)/$($(1)_VER)/),)
$(1)_ROOT=$(DEFAULT_DIR)
else
$(1)_ROOT=$(ROOT)/$(1)/$($(1)_VER)/
endif
endef
$(foreach lib, $(EXTERNAL_DEPS), $(eval $(call set_deps,$(lib))))
$(foreach lib, $(EXTERNAL_DEPS), $(eval $(info $(lib) => $($(lib)_ROOT))))
Make sure to check out the documentation for the eval function.
Also, if you wanted to match against a list of possible directories you could use the following.
define set_deps
$(1)_ROOT = $(firstword $(wildcard $(ROOT)/$(1)/$($(1)_VER)/) $(DEFAULT_DIR))
endef
This site might help:
Note that in the example, the result of the foreach call is what is stored, not the side-effects of calling each function in the foreach loop.
I would like to have the same Makefile for building on Linux and on Windows. I use the default GNU make on Linux and the mingw32-make (also GNU make) on Windows.
I want the Makefile to detect whether it operates on Windows or Linux.
For example make clean command on Windows looks like:
clean:
del $(DESTDIR_TARGET)
But on Linux:
clean:
rm $(DESTDIR_TARGET)
Also I would like to use different directory separator on Windows (\) and Linux (/).
It is possible to detect Windows operating system in Makefile?
PS: I do not want to emulate Linux on Windows (cygwin etc.)
There is similiar question: OS detecting makefile, but I didn't find the answer here.
I solved this by looking for an env variable that will only be set on windows.
ifdef OS
RM = del /Q
FixPath = $(subst /,\,$1)
else
ifeq ($(shell uname), Linux)
RM = rm -f
FixPath = $1
endif
endif
clean:
$(RM) $(call FixPath,objs/*)
Because %OS% is the type of windows, it should be set on all Windows computers but not on Linux.
The blocks then setups up variables for the different programs as well as a function for converting the forward slashes into backslashes.
You to have to use $(call FixPath,path) when you call an outside command (internal commands work fine). You could also use something like:
/ := /
and then
objs$(/)*
if you like that format better.
The SystemRoot trick didn't work for me on Windows XP but this did:
ifeq ($(OS),Windows_NT)
#Windows stuff
...
else
#Linux stuff
....
endif
You should probably use the $(RM) variable to remove some files.
Checking WINDIR or COMSPEC is case-sensitive. Instead, I came up
with the following solution, hope that helps someone someday:
# detect if running under unix by finding 'rm' in $PATH :
ifeq ($(wildcard $(addsuffix /rm,$(subst :, ,$(PATH)))),)
WINMODE=1
else
WINMODE=0
endif
ifeq ($(WINMODE),1)
# native windows setup :
UNLINK = del $(subst /,\,$(1))
CAT = type $(subst /,\,$(1))
else
# cross-compile setup :
UNLINK = $(RM) $(1)
CAT = cat $(1)
endif
I would like to have the same Makefile for building on Linux and on Windows.
Maybe you will like CMake