Unknown Error during synthesis of AXI IPs - verilog

Question

I am attempting to use the IP packaging tools in Xilinx Vivado to create a co-processor with an AXI-Lite interface and utilize it in a Zynq SoC design for my Digital Systems Engineering class. The co-processor is a GCD calculator that we have already developed as part of a previous assignment. I followed the instructor's directions to create an IP out of the GCD calculator, and we loosely followed Tutorial 4A from the PDF located here to create the AXI interface (the I/O declarations are obviously modified to accomodate the GCD calculator). I have a data bus called 'data' running from the AXI IP and the GCD IP to send values to the calculator. However, when I attempt to Synthesize the design, I get an the following error:
[Synth 8-685] variable 'data' should not be used in output port connection'
The error directs to the line of my AXI bus interface instantiation where my data port is defined.
I've been searching online for a solution to this error for hours, but not even the Xilinx website, nor the Xilinx documents that have been made available to us, have any information regarding this error, and I have not been able to find any accounts from anyone experiencing the same error.
I emailed the professor to see if he has any ideas, but he probably won't be awake for another six hours and the assignment is due today (tomorrow?).
Has anyone heard of this error, or have any idea of how to correct it?
Here's a portion of code that contains the error's source:
// Instantiation of Axi Buss Interface S00_AXI
myip_v1.0_0_S00_AVI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) myip_v1_0_S00_AXI_inst (
.done_async(done_async),
.go(go),
.data(data), // The error points to this line
.S_AXI_ACLK(s00_axi_aclk),
... // all remaining ports were generated by the IP tools
);
Thanks,
-Andrew

Answer 1

It looks to me like you are trying to drive a variable from the output of an instantiated module. In Verilog you cannot drive a variable from an instantiated module. This is illegal in Verilog (though it is not in SystemVerilog):
reg OP; -- this is a variable
SOME_MODULE MODULE_INST (.IP(IP), .OP(OP));
whereas this is not illegal:
wire OP; -- this is a net
SOME_MODULE MODULE_INST (.IP(IP), .OP(OP));