Create a lookup table using Verilog ModelSim - verilog
I am trying to create lookup tables that contain 256 elements. I searched a couple of websites and the best way seemed to create a 2D array since a case structure is very long for my application (I will need 7 other tables).
module LUTE1 (clk, address, data);
input clk;
input [7:0] address;
output reg [31:0] data;
reg [31:0] LTE1 [0:255];
The above compiles fine but it gives the error when I add the below.
LTE1 = '{
32'ha5c66363, 32'h84f87c7c, 32'h99ee7777, 32'h8df67b7b, 32'h0dfff2f2, 32'hbdd66b6b, 32'hb1de6f6f, 32'h5491c5c5,
32'h50603030, 32'h03020101, 32'ha9ce6767, 32'h7d562b2b, 32'h19e7fefe, 32'h62b5d7d7, 32'he64dabab, 32'h9aec7676,
32'h458fcaca, 32'h9d1f8282, 32'h4089c9c9, 32'h87fa7d7d, 32'h15effafa, 32'hebb25959, 32'hc98e4747, 32'h0bfbf0f0,
32'hec41adad, 32'h67b3d4d4, 32'hfd5fa2a2, 32'hea45afaf, 32'hbf239c9c, 32'hf753a4a4, 32'h96e47272, 32'h5b9bc0c0,
32'hc275b7b7, 32'h1ce1fdfd, 32'hae3d9393, 32'h6a4c2626, 32'h5a6c3636, 32'h417e3f3f, 32'h02f5f7f7, 32'h4f83cccc,
32'h5c683434, 32'hf451a5a5, 32'h34d1e5e5, 32'h08f9f1f1, 32'h93e27171, 32'h73abd8d8, 32'h53623131, 32'h3f2a1515,
32'h0c080404, 32'h5295c7c7, 32'h65462323, 32'h5e9dc3c3, 32'h28301818, 32'ha1379696, 32'h0f0a0505, 32'hb52f9a9a,
32'h090e0707, 32'h36241212, 32'h9b1b8080, 32'h3ddfe2e2, 32'h26cdebeb, 32'h694e2727, 32'hcd7fb2b2, 32'h9fea7575,
32'h1b120909, 32'h9e1d8383, 32'h74582c2c, 32'h2e341a1a, 32'h2d361b1b, 32'hb2dc6e6e, 32'heeb45a5a, 32'hfb5ba0a0,
32'hf6a45252, 32'h4d763b3b, 32'h61b7d6d6, 32'hce7db3b3, 32'h7b522929, 32'h3edde3e3, 32'h715e2f2f, 32'h97138484,
32'hf5a65353, 32'h68b9d1d1, 32'h00000000, 32'h2cc1eded, 32'h60402020, 32'h1fe3fcfc, 32'hc879b1b1, 32'hedb65b5b,
32'hbed46a6a, 32'h468dcbcb, 32'hd967bebe, 32'h4b723939, 32'hde944a4a, 32'hd4984c4c, 32'he8b05858, 32'h4a85cfcf,
32'h6bbbd0d0, 32'h2ac5efef, 32'he54faaaa, 32'h16edfbfb, 32'hc5864343, 32'hd79a4d4d, 32'h55663333, 32'h94118585,
32'hcf8a4545, 32'h10e9f9f9, 32'h06040202, 32'h81fe7f7f, 32'hf0a05050, 32'h44783c3c, 32'hba259f9f, 32'he34ba8a8,
32'hf3a25151, 32'hfe5da3a3, 32'hc0804040, 32'h8a058f8f, 32'had3f9292, 32'hbc219d9d, 32'h48703838, 32'h04f1f5f5,
32'hdf63bcbc, 32'hc177b6b6, 32'h75afdada, 32'h63422121, 32'h30201010, 32'h1ae5ffff, 32'h0efdf3f3, 32'h6dbfd2d2,
32'h4c81cdcd, 32'h14180c0c, 32'h35261313, 32'h2fc3ecec, 32'he1be5f5f, 32'ha2359797, 32'hcc884444, 32'h392e1717,
32'h5793c4c4, 32'hf255a7a7, 32'h82fc7e7e, 32'h477a3d3d, 32'hacc86464, 32'he7ba5d5d, 32'h2b321919, 32'h95e67373,
32'ha0c06060, 32'h98198181, 32'hd19e4f4f, 32'h7fa3dcdc, 32'h66442222, 32'h7e542a2a, 32'hab3b9090, 32'h830b8888,
32'hca8c4646, 32'h29c7eeee, 32'hd36bb8b8, 32'h3c281414, 32'h79a7dede, 32'he2bc5e5e, 32'h1d160b0b, 32'h76addbdb,
32'h3bdbe0e0, 32'h56643232, 32'h4e743a3a, 32'h1e140a0a, 32'hdb924949, 32'h0a0c0606, 32'h6c482424, 32'he4b85c5c,
32'h5d9fc2c2, 32'h6ebdd3d3, 32'hef43acac, 32'ha6c46262, 32'ha8399191, 32'ha4319595, 32'h37d3e4e4, 32'h8bf27979,
32'h32d5e7e7, 32'h438bc8c8, 32'h596e3737, 32'hb7da6d6d, 32'h8c018d8d, 32'h64b1d5d5, 32'hd29c4e4e, 32'he049a9a9,
32'hb4d86c6c, 32'hfaac5656, 32'h07f3f4f4, 32'h25cfeaea, 32'hafca6565, 32'h8ef47a7a, 32'he947aeae, 32'h18100808,
32'hd56fbaba, 32'h88f07878, 32'h6f4a2525, 32'h725c2e2e, 32'h24381c1c, 32'hf157a6a6, 32'hc773b4b4, 32'h5197c6c6,
32'h23cbe8e8, 32'h7ca1dddd, 32'h9ce87474, 32'h213e1f1f, 32'hdd964b4b, 32'hdc61bdbd, 32'h860d8b8b, 32'h850f8a8a,
32'h90e07070, 32'h427c3e3e, 32'hc471b5b5, 32'haacc6666, 32'hd8904848, 32'h05060303, 32'h01f7f6f6, 32'h121c0e0e,
32'ha3c26161, 32'h5f6a3535, 32'hf9ae5757, 32'hd069b9b9, 32'h91178686, 32'h5899c1c1, 32'h273a1d1d, 32'hb9279e9e,
32'h38d9e1e1, 32'h13ebf8f8, 32'hb32b9898, 32'h33221111, 32'hbbd26969, 32'h70a9d9d9, 32'h89078e8e, 32'ha7339494,
32'hb62d9b9b, 32'h223c1e1e, 32'h92158787, 32'h20c9e9e9, 32'h4987cece, 32'hffaa5555, 32'h78502828, 32'h7aa5dfdf,
32'h8f038c8c, 32'hf859a1a1, 32'h80098989, 32'h171a0d0d, 32'hda65bfbf, 32'h31d7e6e6, 32'hc6844242, 32'hb8d06868,
32'hc3824141, 32'hb0299999, 32'h775a2d2d, 32'h111e0f0f, 32'hcb7bb0b0, 32'hfca85454, 32'hd66dbbbb, 32'h3a2c1616
};
endmodule
The program is giving the following errors:
** Error: (vlog-13069) C:/Modeltech_pe_edu_10.4a/examples/LUTE1.v(9): near "=": syntax error, unexpected '='.
** Error: C:/Modeltech_pe_edu_10.4a/examples/LUTE1.v(9): (vlog-13205) Syntax error found in the scope following 'LTE1'. Is there a missing '::'?
First a quick note: the '{} syntax is SystemVerilog. Verilog can assign a whole array through system task (e.g. $readmemb or PLA modeling task). It cannot assign a whole array in a single assignment.
LTE1 = '{...}; needs to be in an procedural (initial or always block) or continuous assignment (assign statement and must be a wire type, not reg). You can also assign the array in as part of the declaration: logic [31:0] LTE1 [0:255] = '{...};
There's absolutely nothing "wrong" or "inefficient" about using a large case statement to implement a lookup table. The compiler / synthesis tool would implement the same logic as if you were trying to use the huge two-dimensional array (in SystemVerilog).
This is just fine:
case (address)
8'd0: data_temp = 32'ha5c66363;
8'd1: data_temp = 32'h84f87c7c;
8'd2: data_temp = 32'h99ee7777;
...
There's a bit more text in the code for the large case statement, but efficient use of a good text editor (or even a simple script) can simplify the task of actually creating the code.
Related
I get a warning about $readmemh: Too many words in the file
Here is how I define the rom module
module rom(
input wire [31:0] inst_addr_i,
output reg [31:0] inst_o
);
reg [31:0] rom_mem[0:100];
always#(*) begin
inst_o = rom_mem[inst_addr_i>>2];
end
endmodule
Here is the $readmem in tb.v
initial begin
$readmemh("inst.data",tb.rv_soc_ins.rom_ins.rom_mem);
end
And the inst.data file is like this, which has 354 rows.
00000d13
00000d93
00000093
00000113
00208f33
00000e93
00200193
This is what I get when executing the vpp script:
$ vvp a.out
WARNING: tb.v:23: $readmemh(inst.data): Too many words in the file for the requested range [0:100].
VCD info: dumpfile gtk.vcd opened for output.
Although in rom.v, I have set the rom large enough.
reg [31:0] rom_mem[0:100];
The above declaration means that you have a memory with 101 32-bit words.
[0:100] means there are 101 locations (addresses) in the memory.
[31:0] means the memory location (data) is 32 bits wide.
Your inst.data file has 354 rows (or lines) in the file. Each row you showed has one 32-bit data word. Assuming you have one word on each row for the remainder of the file, then you have 354 words in the file.
The warning message tells you that your rom is not large enough to fit all the data words in the file.
I added some comments to the data file to illustrate what Verilog does with the data:
00000d13 // row 1 data loaded into rom_mem[0]
00000d93 // row 2 data loaded into rom_mem[1]
00000093
00000113
...
11111111 // row 100 data loaded into rom_mem[99]
22222222 // row 101 data loaded into rom_mem[100]
33333333 // row 102 data is discarded
...
ffffffff // row 354 data is discarded
As you can see, only the first 101 data words are loaded into the memory. The remaining data words are not used.
If you really want your memory to be 32x101 and you want to get rid of the warning, then you can delete the lines of the file starting at line 102, or you could specify start and end addresses:
$readmemh("inst.data", tb.rv_soc_ins.rom_ins.rom_mem, 0, 101);
If you really want your memory to be 32x354, then you need to change the rom module:
reg [31:0] rom_mem[0:353];
Refer to IEEE Std 1800-2017, section 21.4 Loading memory array data from a file.
The warning is saying that your file (with 354 rows) is longer than your array (with 101 elements). The message about VCD is unconnected: it is simply the next message telling you that the file "gtk.vcd" has been opened.
Confusion About Implementing LeafSystem With Vector Output Port Correctly
I'm a student teaching myself Drake, specifically pydrake with Dr. Russ Tedrake's excellent Underactuated Robotics course. I am trying to write a combined energy shaping and lqr controller for keeping a cartpole system balanced upright. I based the diagram on the cartpole example found in Chapter 3 of Underactuated Robotics [http://underactuated.mit.edu/acrobot.html], and the SwingUpAndBalanceController on Chapter 2: [http://underactuated.mit.edu/pend.html].
I have found that due to my use of the cart_pole.sdf model I have to create an abstract input port due receive FramePoseVector from the cart_pole.get_output_port(0). From there I know that I have to create a control signal output of type BasicVector to feed into a Saturation block before feeding into the cartpole's actuation port.
The problem I'm encountering right now is that I'm not sure how to get the system's current state data in the DeclareVectorOutputPort's callback function. I was under the assumption I would use the LeafContext parameter in the callback function, OutputControlSignal, obtaining the BasicVector continuous state vector. However, this resulting vector, x_bar is always NaN. Out of desperation (and testing to make sure the rest of my program worked) I set x_bar to the controller's initialization cart_pole_context and have found that the simulation runs with a control signal of 0.0 (as expected). I can also set output to 100 and the cartpole simulation just flies off into endless space (as expected).
TL;DR: What is the proper way to obtain the continuous state vector in a custom controller extending LeafSystem with a DeclareVectorOutputPort?
Thank you for any help! I really appreciate it :) I've been teaching myself so it's been a little arduous haha.
# Combined Energy Shaping (SwingUp) and LQR (Balance) Controller
# with a simple state machine
class SwingUpAndBalanceController(LeafSystem):
def __init__(self, cart_pole, cart_pole_context, input_i, ouput_i, Q, R, x_star):
LeafSystem.__init__(self)
self.DeclareAbstractInputPort("state_input", AbstractValue.Make(FramePoseVector()))
self.DeclareVectorOutputPort("control_signal", BasicVector(1),
self.OutputControlSignal)
(self.K, self.S) = BalancingLQRCtrlr(cart_pole, cart_pole_context,
input_i, ouput_i, Q, R, x_star).get_LQR_matrices()
(self.A, self.B, self.C, self.D) = BalancingLQRCtrlr(cart_pole, cart_pole_context,
input_i, ouput_i,
Q, R, x_star).get_lin_matrices()
self.energy_shaping = EnergyShapingCtrlr(cart_pole, x_star)
self.energy_shaping_context = self.energy_shaping.CreateDefaultContext()
self.cart_pole_context = cart_pole_context
def OutputControlSignal(self, context, output):
#xbar = copy(self.cart_pole_context.get_continuous_state_vector())
xbar = copy(context.get_continuous_state_vector())
xbar_ = np.array([xbar[0], xbar[1], xbar[2], xbar[3]])
xbar_[1] = wrap_to(xbar_[1], 0, 2.0*np.pi) - np.pi
# If x'Sx <= 2, then use LQR ctrlr. Cost-to-go J_star = x^T * S * x
threshold = np.array([2.0])
if (xbar_.dot(self.S.dot(xbar_)) < 2.0):
#output[:] = -self.K.dot(xbar_) # u = -Kx
output.set_value(-self.K.dot(xbar_))
else:
self.energy_shaping.get_input_port(0).FixValue(self.energy_shaping_context,
self.cart_pole_context.get_continuous_state_vector())
output_val = self.energy_shaping.get_output_port(0).Eval(self.energy_shaping_context)
output.set_value(output_val)
print(output)
Here are two things that might help: If you want to get the state of the cart-pole from MultibodyPlant, you probably want to be connecting to the continuous_state output port, which gives you a normal vector instead of the abstract-type FramePoseVector. In that case, your call to get_input_port().Eval(context) should work just fine. If you do really want to read the FramePoseVector, then you have to evaluate the input port slightly differently. You can find an example of that here.
reg.coef_ returning same value twice
created a linear regression model in which tried to find the weights(coefficients) and bias(y-intercept) thereby running the following code:- reg.intercept_ reg.coef_ output array([9.41523946, 9.41523946]) array([[-0.44871341, 0.20903483, 0.0142496 , 0.01288174, -0.14055166, -0.17990912, -0.06054988, -0.08992433, -0.1454692 , -0.10144383, -0.20062984, -0.12988747, -0.16859669, -0.12149035, -0.03336798, -0.14690868, 0.32047333], [-0.44871341, 0.20903483, 0.0142496 , 0.01288174, -0.14055166, -0.17990912, -0.06054988, -0.08992433, -0.1454692 , -0.10144383, -0.20062984, -0.12988747, -0.16859669, -0.12149035, -0.03336798, -0.14690868, 0.32047333]]) getting the same values twice rather getting them only once and hence having difficulty in summarizing the weights
It could be that your input provides same columns as input for you reg. model. Can you provide a sample of your dataset?
verilog port mapping syntax error
Error-[SE] Syntax error Following verilog source has syntax error : "design.sv", 5: token is '[' mux4x1 inst1(.sel[0](k), .sel[1](j), .I[0](q), I[1](0), .I[2](1), .I[3](qb), .y(W1)); ^ 1 error
You cannot map a signal to an individual bit of a bus. Instead, you will need to map the concatenation of the signals onto the bus as a whole:
mux4x1 inst1(.sel({k, j}), .I({q, 2'b01, qb}), .y(W1));
Systemverilog code error: near "" gmii_interface": Syntax error, unexpected IDENTIFIER, expecting class
I see a compile error:
// near " gmii_interface": Syntax error, unexpected IDENTIFIER, expecting class"//
in Model SIM when i compile the following testcase.sv code:
`include "D:/users/rajesh/GMII/interface.sv"
`include "D:/users/rajesh/GMII/environment.sv"
program testcase(gmiIInterface tx_intf);
environment env;
initial begin
$display("\n########################################################");
$display("############# Start Verification ##################");
env = new(tx_intf);
env.build();
env.reset();
env.start();
env.waitforend();
env.report();
$display("\############# End Verification ###################");
$display("\#########################################################");
end
endprogram: testcase
the corresponding interface.sv file code is below:
//Component Name: Interface
// Date: June 14, 2014
interface gmii_Interface;
logic tx_en;
logic tx_er;
logic tx_clk;
logic [7:0] tx_data;
logic rx_en;
logic rx_er;
logic rx_clk;
logic [7:0] rx_data;
endinterface : gmii_Interface
I'm a SV beginner, any help would be greatly appreciated.
gmiIInterface is not the same as gmii_Interface.