Systemverilog code error: near "" gmii_interface": Syntax error, unexpected IDENTIFIER, expecting class - verilog

Question

I see a compile error:
// near " gmii_interface": Syntax error, unexpected IDENTIFIER, expecting class"//
in Model SIM when i compile the following testcase.sv code:
`include "D:/users/rajesh/GMII/interface.sv"
`include "D:/users/rajesh/GMII/environment.sv"
program testcase(gmiIInterface tx_intf);
environment env;
initial begin
$display("\n########################################################");
$display("############# Start Verification ##################");
env = new(tx_intf);
env.build();
env.reset();
env.start();
env.waitforend();
env.report();
$display("\############# End Verification ###################");
$display("\#########################################################");
end
endprogram: testcase
the corresponding interface.sv file code is below:
//Component Name: Interface
// Date: June 14, 2014
interface gmii_Interface;
logic tx_en;
logic tx_er;
logic tx_clk;
logic [7:0] tx_data;
logic rx_en;
logic rx_er;
logic rx_clk;
logic [7:0] rx_data;
endinterface : gmii_Interface
I'm a SV beginner, any help would be greatly appreciated.

Answer 1

gmiIInterface is not the same as gmii_Interface.