In the below mentioned verilog code for J-K Flip Flop , i want to initialize wire type q and q_bar with some value. For eg : I am initializing here q and q_bar with 0. But in the output, q and q_bar has don't care (1'hx) value . So how to initialize wire type with constant ?
module JK_FF(j,k,clk,q,q_bar) ;
input j,k,clk ;
output q , q_bar ;
wire s,r,w,z ;
assign w = q ;
assign z = q_bar ;
nand U1(s,j,clk,z) ;
nand U2(r,k,clk,w) ;
nand U3(q,s,z) ;
nand U4(q_bar,r,w) ;
endmodule
/* TEST BENCH */
module JK_FF_TB ;
reg j,k,clk ;
wire q , q_bar ;
assign q = 1'b0 ;
assign q_bar = 1'b0 ;
initial begin
clk = 1'b1 ;
end
JK_FF DUT(j,k,clk,q,q_bar) ;
initial
begin
j = 1'b0 ;
k = 1'b0 ;
#5
j = 1'b0 ;
k = 1'b1 ;
#5
j = 1'b1 ;
k = 1'b0 ;
#5
j = 1'b1 ;
k = 1'b1 ;
end
endmodule
There are several issues to address.
State in Verilog, like flip-flop value, is usually kept in reg type, where the value can be initialized using initial. However, in the simple flip-flop made of gates there are only wires, which can't be initialized.
The design with the crossed NAND gates will in an hardware implementation lead to a stable value at start up, even when the wires are initially undefined 1'bX. You can emulate this in the circuit using conversion from 1'X to 1'b0 or 1'b1 at q and q_bar using assign as:
assign w = q !== 1'b0; // 1'bX => 1
assign z = q_bar === 1'b1; // 1'bX => 0
The Verilog implementation will however give a race condition, since the clock pulse will always be too long for the immediate change that occur if this design is simulated. This is typically shown as an infinite iteration during simulation, thereby reaching iteration limits with resulting error.
So more modifications are required, and you can find a great tutorial here: The JK Flip Flop
Related
I made 4_to_1 MUX with 2_to_1 MUX. I used always syntax. The output is delayed one time unit, but I don't know why.
When I change the always condition of 4_to_1 MUX's module sel to *, it works well. Why is this working?
module MUX_2_to_1 (
a0,a1,sel,out);
input [3:0]a0;
input [3:0]a1;
input sel;
output reg [3:0]out;
always #(sel)
begin
if (sel == 0)
out <= a0;
else if (sel == 1)
out <= a1;
end
endmodule
*
module MUX_4_to_1(
x0,x1,x2,x3,sel,out);
input [3:0]x0;
input [3:0]x1;
input [3:0]x2;
input [3:0]x3;
input [1:0]sel;
output reg [3:0]out;
wire [3:0]w0;
wire [3:0]w1;
MUX_2_to_1 m0 (x0,x1,sel[0],w0);
MUX_2_to_1 m1 (x2,x3,sel[0],w1);
always #(sel)
begin
if(sel[1] == 0)
out <= w0;
else if (sel[1] == 1)
out <= w1;
end
endmodule
*
`timescale 100ps/1ps
module Testbench_Mux;
reg [3:0]x0;
reg [3:0]x1;
reg [3:0]x2;
reg [3:0]x3;
reg [1:0]sel;
wire [3:0]out;
MUX_4_to_1 m0 (x0,x1,x2,x3,sel,out);
initial
begin
x0 = 4'b0001; x1 = 4'b0010; x2 = 4'b0100; x3 = 4'b1000;
#0 sel = 2'b00;
#5 sel = 2'b01;
#5 sel = 2'b10;
#5 sel = 2'b11;
#5 $stop;
end
endmodule
You are not using recommended Verilog coding practices for combinational logic. One problem is that you used an incomplete sensitivity list:
always #(sel)
Since there are 2 other signals, w0 and w1, which are read in the always block, they must also be in the sensitivity list. The verbose way to do this is:
always #(sel or w0 or w1)
The preferred way to do this is to use the compact * syntax:
always #(*)
This assures that the always block will be triggered when any change occurs to any signal read in the block.
Another issue is that you should always use blocking assignments for combinational logic. There is ample documentation out there as to the reason.
Change <= to =:
always #(*)
begin
if(sel[1] == 0)
out = w0;
else if (sel[1] == 1)
out = w1;
end
If you don't follow these recommendations, you get undesired simulation results.
You should change your MUX_2_to_1 module as well.
This is LSFR of 10 bits. I instentiated LSFR module in verilog. you can see in the given code below . the output of LSFR is Current State. i want to access each of its individual bits. but here i am getting 0 for Current_State. it is not updating. please any one can help me ..
module LSFR_counter #(parameter n=6)( output Reg, input clk, input reset);
//parameter n=10; // Change more than n to change LFSR length.
reg [n:1]Reg; //All procedure outputs must be registered
reg [n:1] counter ;
initial
counter =0 ;
always #(posedge clk or posedge reset)
if
(reset) Reg <=1;
else
begin
counter <= counter+1 ;
Reg <= {Reg[n-1:2], Reg[n]^Reg[1], Reg[n]};
end
endmodule
module Main( output Reg input Clock , input reset
);
reg Fgf8,Emx2,Pax6,Coup_tfi,Sp8; // Genes
reg F,E,P,C,S; // Proteins
reg [10:1] Current_State ;
LSFR_counter #(.n(10)) lsfr ( .Reg (Current_State), .clk (Clock ), .reset(reset) ) ;
Fgf8 <= Current_State[N-0] ; // Gene
F <= Current_State[N-1] ; // Protein
Emx2 <= Current_State[N-2] ;
E <= Current_State[N-3] ;
Pax6 <= Current_State[N-4] ;
P <= Current_State[N-5] ;
Coup_tfi <= Current_State[N-6] ;
C <= Current_State[N-7] ;
Sp8 <= Current_State[N-8] ;
S <= Current_State[N-9] ;
endmodule ;
Several problems in the code presented:
The Main module has an output named Reg, which is not assigned any signal. So if you are expecting to get any value out of it, you won't.
The signals Fgf8, F.. and friends are assigned, but not used. Update: Actully the assignment is incorrect. If they are supposed to be assigned synchronously (on clock cycles), it should be wrapped in always block. If you mean to have a combinatorial circuit instead, you should use the assign statement.
The variable/signal N is not defined. Verilog is case-sensitive, so n != N.
in the LSFR_counter module, the counter is not reset to initial value.
These are problems that can be seen so far.
In LSFR_counter: you are mixing ANSI and non-ANSI header styles. This is illegal syntax. Maybe your simulator/synthesizer is allowing it, but it is not supported and a bad practice.
You should use ANSI: IEEE Std 1800-2012 § 23.2.2.2 ANSI style list of port declarations
module LSFR_counter #(parameter n=6)( output reg [n:1] Reg, input clk, input reset);
reg [n:1] counter;
// ...
or non-ANSI: IEEE Std 1800-2012 § 23.2.2.1 Non-ANSI style port declarations
module LSFR_counter #(parameter n=6)( Reg, clk, reset);
output Reg;
input clk;
input reset;
reg [n:1] Reg;
reg [n:1] counter;
// ...
Non-ANSI is for IEEE Std 1364-1995 and backward comparability with In later versions of IEEE 1364 and all versions of IEEE 1800. Support for ANSI existed since IEEE Std 1364-2001.
In Main: Nothing is driving Reg. The other signals (eg: Fgf8, F, Emx2, etc.) are never declared and have illegal assignment. N is also never defined. I'll assume it is a parameter. You may declare them as reg and assign in a combinational block:
parameter N=10;
reg Fgf8,F, ... ,Sp8,S;
always #* begin
Fgf8 = Current_State[N-0] ; // Gene
F = Current_State[N-1] ; // Protein
// ...
Sp8 = Current_State[N-8] ;
S = Current_State[N-9] ;
end
Or declare as wires and assign with continuous assignment:
parameter N=10;
wire Fgf8 = Current_State[N-0] ; // Gene
wire F = Current_State[N-1] ; // Protein
// ...
wire Sp8 = Current_State[N-8] ;
wire S = Current_State[N-9] ;
Both with synthesize the same.
Can you tell me why this simple verilog program doesn't print 4 as I want?
primitive confrontatore(output z, input x, input y);
table
0 0 : 1;
0 1 : 0;
1 0 : 0;
1 1 : 1;
endtable
endprimitive
comparatore :
module comparatore (r, x, y);
output wire r;
input wire [21:0]x;
input wire [21:0]y;
wire [21:0]z;
genvar i;
generate
for(i=0; i<22; i=i+1)
begin
confrontatore t(z[i],x[i],y[i]);
end
endgenerate
assign r = & z;
endmodule
commutatore :
module commutatore (uscita_commutatore, alpha);
output wire [2:0]uscita_commutatore;
input wire alpha;
reg [2:0]temp;
initial
begin
case (alpha)
1'b0 : assign temp = 3;
1'b1 : assign temp = 4;
endcase
end
assign uscita_commutatore = temp;
endmodule
prova:
module prova();
reg [21:0]in1;
reg [21:0]in2;
wire [2:0]uscita;
wire uscita_comparatore;
comparatore c(uscita_comparatore, in1, in2);
commutatore C(uscita, uscita_comparatore);
initial
begin
in1 = 14;
$dumpfile("prova.vcd");
$dumpvars;
$monitor("\n in1 %d in2 %d -> uscita %d uscita_comparatore %d \n", in1, in2, uscita, uscita_comparatore);
#25 in2 = 14;
#100 $finish;
end
endmodule
The issue is in commutatore. You are using initial, which means the procedural block is only executed at time 0. At time 0, the input alpha is 1'bx, meaning temp is not assigned to anything. Instead of initial, use always #* which will execute the procedural block every time alpha changes.
Generally you should not assign statements in procedural blocks. It is legal Verilog however it is often the source of design bugs and synthesis support is limited.
always #*
begin
case (alpha)
1'b0 : temp = 3;
1'b1 : temp = 4;
default: temp = 3'bx; // <-- optional : to catch known to unknown transitions
endcase
end
The reason you are not getting 4 as you expect for an output is because your commutatore uses an initial block with assign statements in it when you wanted an always #* block to perform the combinational logic to get temp. initial blocks only fire once at the beginning of a simulation, while you want continuous assignment to act as combinational logic. Also, the assign statements in the block are not needed, they only make the simulation behave improperly for your purposes (typically, you will never need to use assign inside another block (initial,always,etc) as this has another meaning than simply set x to y.
For example, you really want something like this:
always #(*) begin
case (alpha)
1'b0: temp = 3'd3;
1'b1: temp = 3'd4;
endcase
end
Also, Verilog already has a build XNOR primative so your confrontatore is not needed, you can use xnor instead.
I have a Verilog project below that implements an LSFR. Currently, the code does not compile correctly in Xilinx ISE 14.6. It errors out with:
ERROR:HDLCompilers:108 - "top.v" line 70 Part-select of scalar wire array 'q' is illegal
ERROR:HDLCompilers:107 - "top.v" line 70 Illegal right hand side of nonblocking assignment
ERROR:HDLCompilers:108 - "top.v" line 74 Part-select of scalar wire array 'q' is illegal
ERROR:HDLCompilers:107 - "top.v" line 74 Illegal right hand side of nonblocking assignment
Which is pointing at this point in my code:
always # (display) begin
if(display == 1'b0) begin
LSB <= q[3:0];
switch <= LSB;
end
else begin
MSB <= q[7:4];
switch <= MSB;
end
end
I looked up the error in the Xilinx user guide, and it says to resolve the issue, give the value a bit width greater than 2. Since it's already at 8, I'm not sure what's wrong.
Here's my entire top module:
`timescale 1ns / 1ps
module top (c, start, clk_in, display, segments);
input [7:0] c;
input start, clk_in;
output [3:0] display;
output [6:0] segments;
reg [6:0] segments;
reg [3:0] display;
reg [3:0] LSB;
reg [3:0] MSB;
wire q[7:0];
wire q_[7:0];
wire clk, dff0_w, dff1_w, dff2_w, dff3_w, dff4_w, dff5_w, dff6_w;
reg [3:0] switch;
initial begin
display <= 4'b0111;
end
clock_divider #(15) divider(.cin(clk_in), .cout(clk));
//switch changes back and forth between the MSB and LSB of the 8 bit number when muxing
decoder bits(clk, switch, segments);
//D adders
dff dff0(.D(dff0_w),.Q(q[0]),.clk(clk),.start(start));
dff dff1(q[0],q[1],clk,start);
dff dff2(q[1],q[2],clk,start);
dff dff3(q[2],q[3],clk,start);
dff dff4(q[3],q[4],clk,start);
dff dff5(q[4],q[5],clk,start);
dff dff6(q[5],q[6],clk,start);
dff dff7(q[6],q[7],clk,start);
//xor gates
xor (dff6_w, q[7], q_[6]);
xor (dff5_w, dff6_w, q_[5]);
xor (dff4_w, dff5_w, q_[4]);
xor (dff3_w, dff4_w, q_[3]);
xor (dff2_w, dff3_w, q_[2]);
xor (dff1_w, dff2_w, q_[1]);
xor (dff0_w, dff1_w, q_[0]);
//buffer the C values
assign q_[0] = c[0] ? 1'b0 : q[0];
assign q_[1] = c[1] ? 1'b0 : q[1];
assign q_[2] = c[2] ? 1'b0 : q[2];
assign q_[3] = c[3] ? 1'b0 : q[3];
assign q_[4] = c[4] ? 1'b0 : q[4];
assign q_[5] = c[5] ? 1'b0 : q[5];
assign q_[6] = c[6] ? 1'b0 : q[6];
assign q_[7] = 1 ? 1'b0 : q[7]; //Cn is always 1
//mux the display
always # (posedge clk) begin
if(display == 4'b0111)
display <= 4'b1011;
else
display <= 4'b0111;
end
//display the appropriate value when the anode is asserted
always # (display) begin
if(display == 1'b0) begin
LSB <= q[3:0];
switch <= LSB;
end
else begin
MSB <= q[7:4];
switch <= MSB;
end
end
endmodule
Try changing:
wire q[7:0];
wire q_[7:0];
to:
wire [7:0] q;
wire [7:0] q_;
That clears up compile errors for me.
I have the following Verilog code:
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2010 www.xilinx.com
//
// XAPP xxx - 1:5 Differential Data De-serializer
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : serdes_1_to_5_diff_data.v
//
// Description : This module instantiates IODELAY2 and ISERDES2 primitives
// to receive TMDS differential data in 1:5 format
//
// Note:
//
// Author : Bob Feng
//////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module serdes_1_to_5_diff_data # (
parameter DIFF_TERM = "TRUE",
parameter SIM_TAP_DELAY = 49,
parameter BITSLIP_ENABLE = "FALSE"
)(
input wire use_phase_detector, // '1' enables the phase detector logic
input wire datain_p, // Input from LVDS receiver pin
input wire datain_n, // Input from LVDS receiver pin
input wire rxioclk, // IO Clock network
input wire rxserdesstrobe, // Parallel data capture strobe
input wire reset, // Reset line
input wire gclk, // Global clock
input wire bitslip, // Bitslip control line
output wire [4:0] data_out // Output data
);
wire ddly_m;
wire ddly_s;
wire busys;
wire rx_data_in;
wire cascade;
wire pd_edge;
reg [8:0] counter;
reg [3:0] state;
reg cal_data_sint;
wire busy_data;
reg busy_data_d;
wire cal_data_slave;
reg enable;
reg cal_data_master;
reg rst_data;
reg inc_data_int; //THIS LINE (81) IS CAUSING THE ERROR
wire inc_data;
reg ce_data;
reg valid_data_d;
reg incdec_data_d;
reg [4:0] pdcounter;
wire valid_data;
wire incdec_data;
reg flag;
reg mux;
reg ce_data_inta ;
wire [1:0] incdec_data_or;
wire incdec_data_im;
wire [1:0] valid_data_or;
wire valid_data_im;
wire [1:0] busy_data_or;
wire all_ce;
wire [1:0] debug_in = 2'b00;
assign busy_data = busys ;
assign cal_data_slave = cal_data_sint ;
/////////////////////////////////////////////////
//
// IDELAY Calibration FSM
//
/////////////////////////////////////////////////
always # (posedge gclk or posedge reset)
begin
if (reset == 1'b1) begin
state <= 0 ;
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
counter <= 9'h000 ;
enable <= 1'b0 ;
mux <= 1'h1 ;
end
else begin
counter <= counter + 9'h001 ;
if (counter[8] == 1'b1) begin
counter <= 9'h000 ;
end
if (counter[5] == 1'b1) begin
enable <= 1'b1 ;
end
if (state == 0 && enable == 1'b1) begin // Wait for IODELAY to be available
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
rst_data <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 1 ;
end
end
else if (state == 1) begin // Issue calibrate command to both master and slave, needed for simulation, not for the silicon
cal_data_master <= 1'b1 ;
cal_data_sint <= 1'b1 ;
if (busy_data_d == 1'b1) begin // and wait for command to be accepted
state <= 2 ;
end
end
else if (state == 2) begin // Now RST master and slave IODELAYs needed for simulation, not for the silicon
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
if (busy_data_d == 1'b0) begin
rst_data <= 1'b1 ;
state <= 3 ;
end
end
else if (state == 3) begin // Wait for IODELAY to be available
rst_data <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 4 ;
end
end
else if (state == 4) begin // Wait for occasional enable
if (counter[8] == 1'b1) begin
state <= 5 ;
end
end
else if (state == 5) begin // Calibrate slave only
if (busy_data_d == 1'b0) begin
cal_data_sint <= 1'b1 ;
state <= 6 ;
end
end
else if (state == 6) begin // Wait for command to be accepted
cal_data_sint <= 1'b0 ;
if (busy_data_d == 1'b1) begin
state <= 7 ;
end
end
else if (state == 7) begin // Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 4 ;
end
end
end
end
always # (posedge gclk or posedge reset) // Per-bit phase detection state machine
begin
if (reset == 1'b1) begin
pdcounter <= 5'b1000 ;
ce_data_inta <= 1'b0 ;
flag <= 1'b0 ; // flag is there to only allow one inc or dec per cal (test)
end
else begin
busy_data_d <= busy_data_or[1] ;
if (use_phase_detector == 1'b1) begin // decide whther pd is used
incdec_data_d <= incdec_data_or[1] ;
valid_data_d <= valid_data_or[1] ;
if (ce_data_inta == 1'b1) begin
ce_data = mux ;
end
else begin
ce_data = 64'h0000000000000000 ;
end
if (state == 7) begin
flag <= 1'b0 ;
end
else if (state != 4 || busy_data_d == 1'b1) begin // Reset filter if state machine issues a cal command or unit is busy
pdcounter <= 5'b10000 ;
ce_data_inta <= 1'b0 ;
end
else if (pdcounter == 5'b11111 && flag == 1'b0) begin // Filter has reached positive max - increment the tap count
ce_data_inta <= 1'b1 ;
inc_data_int <= 1'b1 ;
pdcounter <= 5'b10000 ;
flag <= 1'b1 ;
end
else if (pdcounter == 5'b00000 && flag == 1'b0) begin // Filter has reached negative max - decrement the tap count
ce_data_inta <= 1'b1 ;
inc_data_int <= 1'b0 ;
pdcounter <= 5'b10000 ;
flag <= 1'b1 ;
end
else if (valid_data_d == 1'b1) begin // increment filter
ce_data_inta <= 1'b0 ;
if (incdec_data_d == 1'b1 && pdcounter != 5'b11111) begin
pdcounter <= pdcounter + 5'b00001 ;
end
else if (incdec_data_d == 1'b0 && pdcounter != 5'b00000) begin // decrement filter
pdcounter <= pdcounter + 5'b11111 ;
end
end
else begin
ce_data_inta <= 1'b0 ;
end
end
else begin
ce_data = all_ce ;
inc_data_int = debug_in[1] ;
end
end
end
assign inc_data = inc_data_int ;
assign incdec_data_or[0] = 1'b0 ; // Input Mux - Initialise generate loop OR gates
assign valid_data_or[0] = 1'b0 ;
assign busy_data_or[0] = 1'b0 ;
assign incdec_data_im = incdec_data & mux; // Input muxes
assign incdec_data_or[1] = incdec_data_im | incdec_data_or; // AND gates to allow just one signal through at a tome
assign valid_data_im = valid_data & mux; // followed by an OR
assign valid_data_or[1] = valid_data_im | valid_data_or; // for the three inputs from each PD
assign busy_data_or[1] = busy_data | busy_data_or; // The busy signals just need an OR gate
assign all_ce = debug_in[0] ;
IBUFDS #(
.DIFF_TERM (DIFF_TERM))
data_in (
.I (datain_p),
.IB (datain_n),
.O (rx_data_in)
);
//
// Master IDELAY
//
IODELAY2 #(
.DATA_RATE ("SDR"),
.IDELAY_VALUE (0),
.IDELAY2_VALUE (0),
.IDELAY_MODE ("NORMAL" ),
.ODELAY_VALUE (0),
.IDELAY_TYPE ("DIFF_PHASE_DETECTOR"),
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT"), //("WRAPAROUND"),
.DELAY_SRC ("IDATAIN"),
.SERDES_MODE ("MASTER"),
.SIM_TAPDELAY_VALUE (SIM_TAP_DELAY)
) iodelay_m (
.IDATAIN (rx_data_in), // data from IBUFDS
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_m), // Output data 1 to ILOGIC/ISERDES2
.DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2
.IOCLK0 (rxioclk), // High speed clock for calibration
.IOCLK1 (1'b0), // High speed clock for calibration
.CLK (gclk), // Fabric clock (GCLK) for control signals
.CAL (cal_data_master), // Calibrate control signal
.INC (inc_data), // Increment counter
.CE (ce_data), // Clock Enable
.RST (rst_data), // Reset delay line
.BUSY () // output signal indicating sync circuit has finished / calibration has finished
);
//
// Slave IDELAY
//
IODELAY2 #(
.DATA_RATE ("SDR"),
.IDELAY_VALUE (0),
.IDELAY2_VALUE (0),
.IDELAY_MODE ("NORMAL" ),
.ODELAY_VALUE (0),
.IDELAY_TYPE ("DIFF_PHASE_DETECTOR"),
.COUNTER_WRAPAROUND ("WRAPAROUND"),
.DELAY_SRC ("IDATAIN"),
.SERDES_MODE ("SLAVE"),
.SIM_TAPDELAY_VALUE (SIM_TAP_DELAY)
) iodelay_s (
.IDATAIN (rx_data_in), // data from IBUFDS
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_s), // Slave output data to ILOGIC/ISERDES2
.DATAOUT2 (), //
.IOCLK0 (rxioclk), // High speed IO clock for calibration
.IOCLK1 (1'b0),
.CLK (gclk), // Fabric clock (GCLK) for control signals
.CAL (cal_data_slave), // Calibrate control signal
.INC (inc_data), // Increment counter
.CE (ce_data), // Clock Enable
.RST (rst_data), // Reset delay line
.BUSY (busys) // output signal indicating sync circuit has finished / calibration has finished
);
//
// Master ISERDES
//
ISERDES2 #(
.DATA_WIDTH (5),
.DATA_RATE ("SDR"),
.BITSLIP_ENABLE (BITSLIP_ENABLE),
.SERDES_MODE ("MASTER"),
.INTERFACE_TYPE ("RETIMED"))
iserdes_m (
.D (ddly_m),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rxserdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.SHIFTIN (pd_edge),
.BITSLIP (bitslip),
.FABRICOUT (),
.Q4 (data_out[4]),
.Q3 (data_out[3]),
.Q2 (data_out[2]),
.Q1 (data_out[1]),
.DFB (),
.CFB0 (),
.CFB1 (),
.VALID (valid_data),
.INCDEC (incdec_data),
.SHIFTOUT (cascade));
//
// Slave ISERDES
//
ISERDES2 #(
.DATA_WIDTH (5),
.DATA_RATE ("SDR"),
.BITSLIP_ENABLE (BITSLIP_ENABLE),
.SERDES_MODE ("SLAVE"),
.INTERFACE_TYPE ("RETIMED")
) iserdes_s (
.D (ddly_s),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rxserdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.SHIFTIN (cascade),
.BITSLIP (bitslip),
.FABRICOUT (),
.Q4 (data_out[0]),
.Q3 (),
.Q2 (),
.Q1 (),
.DFB (),
.CFB0 (),
.CFB1 (),
.VALID (),
.INCDEC (),
.SHIFTOUT (pd_edge));
reg [7:0] rxpdcntr = 8'h7f;
always # (posedge gclk or posedge reset) begin
if (reset)
rxpdcntr <= 8'h7f;
else if (ce_data)
if (inc_data)
rxpdcntr <= rxpdcntr + 1'b1;
else
rxpdcntr <= rxpdcntr - 1'b1;
end
endmodule
I keep getting the following error when I try to generate a netlist for this design in Xilinx Platform Studio:
ERROR:HDLCompiler:1511 - "/home/eamorr/Desktop/Dropbox/UCD/digitalEye/Atlys_HDMI_PLB_demo/project/pcores/hdmi_in_v1_00_a/hdl/verilog/serdes_1_to_5_diff_data.v" Line 82: Mix of blocking and non-blocking assignments to variable <inc_data_int> is not a recommended coding practice.
ERROR:EDK:546 - Aborting XST flow execution!
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/system_microblaze_0_wrapper.ngc] Error 2
I'm totally stuck and don't know what to do.
For inferring sequential logic for synthesis, you should use nonblocking assignments (<=) instead of blocking assignments (=). For example, change:
ce_data = mux ;
to:
ce_data <= mux ;
That is from the HDMI example on the website digilentic I assume.
Look at all the inc_data_int assignments:
inc_data_int <= 1'b1 ;
inc_data_int <= 1'b0 ;
inc_data_int = debug_in[1] ;
I would comment out the last one since I assume it is for debugging purposes.
(I got the HDMI working like that.)