how can i used the output of the instentiated module in verilog? - verilog

Question

This is LSFR of 10 bits. I instentiated LSFR module in verilog. you can see in the given code below . the output of LSFR is Current State. i want to access each of its individual bits. but here i am getting 0 for Current_State. it is not updating. please any one can help me ..
module LSFR_counter #(parameter n=6)( output Reg, input clk, input reset);
//parameter n=10; // Change more than n to change LFSR length.
reg [n:1]Reg; //All procedure outputs must be registered
reg [n:1] counter ;
initial
counter =0 ;
always #(posedge clk or posedge reset)
if
(reset) Reg <=1;
else
begin
counter <= counter+1 ;
Reg <= {Reg[n-1:2], Reg[n]^Reg[1], Reg[n]};
end
endmodule
module Main( output Reg input Clock , input reset
);
reg Fgf8,Emx2,Pax6,Coup_tfi,Sp8; // Genes
reg F,E,P,C,S; // Proteins
reg [10:1] Current_State ;
LSFR_counter #(.n(10)) lsfr ( .Reg (Current_State), .clk (Clock ), .reset(reset) ) ;
Fgf8 <= Current_State[N-0] ; // Gene
F <= Current_State[N-1] ; // Protein
Emx2 <= Current_State[N-2] ;
E <= Current_State[N-3] ;
Pax6 <= Current_State[N-4] ;
P <= Current_State[N-5] ;
Coup_tfi <= Current_State[N-6] ;
C <= Current_State[N-7] ;
Sp8 <= Current_State[N-8] ;
S <= Current_State[N-9] ;
endmodule ;

Answer 1

Several problems in the code presented:
The Main module has an output named Reg, which is not assigned any signal. So if you are expecting to get any value out of it, you won't.
The signals Fgf8, F.. and friends are assigned, but not used. Update: Actully the assignment is incorrect. If they are supposed to be assigned synchronously (on clock cycles), it should be wrapped in always block. If you mean to have a combinatorial circuit instead, you should use the assign statement.
The variable/signal N is not defined. Verilog is case-sensitive, so n != N.
in the LSFR_counter module, the counter is not reset to initial value.
These are problems that can be seen so far.

Answer 2

In LSFR_counter: you are mixing ANSI and non-ANSI header styles. This is illegal syntax. Maybe your simulator/synthesizer is allowing it, but it is not supported and a bad practice.
You should use ANSI: IEEE Std 1800-2012 § 23.2.2.2 ANSI style list of port declarations
module LSFR_counter #(parameter n=6)( output reg [n:1] Reg, input clk, input reset);
reg [n:1] counter;
// ...
or non-ANSI: IEEE Std 1800-2012 § 23.2.2.1 Non-ANSI style port declarations
module LSFR_counter #(parameter n=6)( Reg, clk, reset);
output Reg;
input clk;
input reset;
reg [n:1] Reg;
reg [n:1] counter;
// ...
Non-ANSI is for IEEE Std 1364-1995 and backward comparability with In later versions of IEEE 1364 and all versions of IEEE 1800. Support for ANSI existed since IEEE Std 1364-2001.
In Main: Nothing is driving Reg. The other signals (eg: Fgf8, F, Emx2, etc.) are never declared and have illegal assignment. N is also never defined. I'll assume it is a parameter. You may declare them as reg and assign in a combinational block:
parameter N=10;
reg Fgf8,F, ... ,Sp8,S;
always #* begin
Fgf8 = Current_State[N-0] ; // Gene
F = Current_State[N-1] ; // Protein
// ...
Sp8 = Current_State[N-8] ;
S = Current_State[N-9] ;
end
Or declare as wires and assign with continuous assignment:
parameter N=10;
wire Fgf8 = Current_State[N-0] ; // Gene
wire F = Current_State[N-1] ; // Protein
// ...
wire Sp8 = Current_State[N-8] ;
wire S = Current_State[N-9] ;
Both with synthesize the same.