I have implemented a 4x16 Decoder using Verilog along with it's test. For each case the decoder should output a 16-bit digit with only one of the bits high. I can't manage to get all the desired outputs when I run the program. Here is the code for the Decoder and test, and the output at the console:
4x16 Decoder:
module Decoder4x16 (input [3:0] select, input enable, output reg [16:0] out);
always #(select, enable)
begin
if(enable == 1'b0)
out = 16'b0000000000000000;
else if(enable == 1'b1)
if(select == 4'b0000)
out <= 16'b0000000000000001;
else if(select == 4'b0001)
out <= 16'b0000000000000010;
else if(select == 4'b0010)
out <= 16'b0000000000000100;
else if(select == 4'b0011)
out <= 16'b0000000000001000;
else if(select == 4'b0100)
out <= 16'b0000000000010000;
else if(select == 4'b0101)
out <= 16'b0000000000100000;
else if(select == 4'b0110)
out <= 16'b0000000001000000;
else if(select == 4'b0111)
out <= 16'b0000000010000000;
else if(select == 4'b1000)
out <= 16'b0000000100000000;
else if(select == 4'b1001)
out <= 16'b0000001000000000;
else if(select == 4'b1010)
out <= 16'b0000010000000000;
else if(select == 4'b1011)
out <= 16'b0000100000000000;
else if(select == 4'b1100)
out <= 16'b0001000000000000;
else if(select == 4'b1101)
out <= 16'b0010000000000000;
else if(select == 4'b111)
out <= 16'b0100000000000000;
else if(select == 4'b1111)
out <= 16'b1000000000000000;
end
endmodule
Test:
module Decoder4x16_test;
reg [3:0] select;
reg enable;
wire [16:0] out;
parameter sim_time = 2800;
Decoder4x16 decoder(select, enable, out);
initial #sim_time $finish;
initial
begin
select = 4'b0000;
enable = 1'b0;
repeat(16) #10 begin
enable = 1'b1;
#85 $display("select = %b \t out = %b", select, out);
select = select + 4'b0001;
end
end
endmodule
When I run the program it outputs the correct output until it reaches the test case where the input is 1101. After that the decoder outputs the wrong value that it is suppose to display. Here is the output:
select = 0000 out = 00000000000000001
select = 0001 out = 00000000000000010
select = 0010 out = 00000000000000100
select = 0011 out = 00000000000001000
select = 0100 out = 00000000000010000
select = 0101 out = 00000000000100000
select = 0110 out = 00000000001000000
select = 0111 out = 00000000010000000
select = 1000 out = 00000000100000000
select = 1001 out = 00000001000000000
select = 1010 out = 00000010000000000
select = 1011 out = 00000100000000000
select = 1100 out = 00001000000000000
select = 1101 out = 00010000000000000
select = 1110 out = 00010000000000000
select = 1111 out = 01000000000000000
Here, out is a reg that means it holds a value that is assigned to it. There is no else if condition for select=4'b1110. So, out holds or retains its previous value which was from select=4'b1101. That is, out holds value 00010000000000000 which is displayed.
So, add an else if condition for select=4'b1110 and the code works fine.
else if(select == 4'b1110)
out <= 16'b0100000000000000;
Moreover, a decoder is purely combinational circuit. While creating any combinational logic, the use of blocking assignments(=) is preferred. So, use the following syntax.
else if(select == 4'b1110)
out = 16'b0100000000000000; // blocking
One more thing just to elaborate, use always#(*) instead of manual sensitivity list. This will help reducing confusion of sensitivity lists.
Try this simple code,
module Decoder4x16 (input [3:0] select,
input enable,
output wire [16:0] out);
assign out = {17{enable}} & (1'b1 << select);
endmodule
Synthesized in ISE too.
Related
[These are the errors I keep getting][1]
I cant seen to figure out what is causing these errors I have looked them up several times but I have not found a clear solution. I am not sure what is wrong with my define statement and why I am told I am missing a "X:X". I thought that I had already declared the reg which_seven properly. Thank you for looking at my post.
[1]: https://i.stack.imgur.com/orCVx.png
`define Ka = 7'b1111000 // seven
`define Kb = 7'b0000000 // eight
`define Kc = 7'b1111001 // one
`define Kd = 7'b0100100 // two
`define Ke = 7'b0110000 // three
`define first = 2'b00 // first seven
`define second = 2'b01 // second seven
module lab4_top(SW,KEY,HEX0);
input [9:0] SW;
input [3:0] KEY;
output [6:0] HEX0;
reg[6:0] present_state;
reg [1:0] which_seven;
always #(KEY == 4'b0000) begin
if (KEY == 4'b0010 || KEY == 4'b0011)
present_state = 7'b1111000;
which_seven = `first;
end
else begin
case(present_state)
`Ka: if (SW == 9'b000000000) begin
if(which_seven == `first) begin
present_state = `Ka; // if present_state is 7
which_seven = `second;
end
else
present_state = `Kb;
else begin
if(which_seven == `first) begin
present_state = `Ke;
end
else begin
present_state = `Ka;
which_seven = `second;
end
end
end
`Kb: if (SW == 9'b000000000)
present_state = `Kc; // if present_state is 8
else
present_state = `Ka;
`Kc: if (SW == 9'b000000000)
present_state = `Kd; // if present_state is 1
else
present_state = `Kb;
`Kd: if (SW == 9'b000000000)
present_state = `Ke; // if present_state is 2
else
present_state = `Kc;
`Ke: if (SW == 9'b000000000) begin
present_state = `Ka; // if present_state is 3
which_seven = `first;
end
else
present_state = `Kd;
default: present_state = 7'bXXXXXXX;
endcase
case(present_state)
`Ka: HEX0 = 7'b1111000; // seven
`Kb: HEX0 = 7'b0000000; // eight
`Kc: HEX0 = 7'b1111001; // one
`Kd: HEX0 = 7'b0100100; // two
`Ke: HEX0 = 7'b0110000; // three
default: HEX0 = 7'bXXXXXXX;
endcase
end
endmodule
I didn't check your logic. Just find some errors here.
When you use `define, don't add the equal sign =. (= is needed in parameter statement)Modify it to :
`define Ka 7'b1111000 // seven
HEX0 is used in a always block, so it should be declared as reg.
reg [6:0] HEX0;
The always #(KEY == 4'b0000) statement is wrong.To save your life, just use the following easier way.
always#(*)
The if-else and begin-end is no paired in the always block.Only you know the logic. So check and correct them. Sometimes maintaining a good code indent will help you a lot.
SW is declared as a 10-bit signal, but is compared with a 9-bit zero. It's ok, but any lint tool will throw a warning message.
How can I check for a parameter based value in an if statement?
I have a parametrized counter and I cannot find answers to how to check the max size i.e. e.g.
if(count_val == WIDTH'b1) count_pulse = 1'b1;
Any chance i could get some help :) ?
module counter #(
parameter WIDTH=3,
parameter DIR = 0
)(CLK, EN, RST, COUNT_VAL, COUNT_PULSE);
input CLK, EN, RST;
output [WIDTH:0] COUNT_VAL;
output COUNT_PULSE;
reg[WIDTH:0] count_val=0;
reg count_pulse;
always #(posedge CLK)
begin
if(RST == 1'b1) count_val <= 0;
else if(EN == 1'b1) begin
if(DIR == 1'b0) count_val <= count_val + 1;
else if(DIR == 1'b1) count_val <= count_val - 1;
if(count_val == WIDTH'b1) count_pulse = 1'b1;
else count_pulse = 1'b0;
end
end
assign COUNT_VAL = count_val;
endmodule
You can use a replication.
if(count_val == {WIDTH{1'b1}}) count_pulse = 1'b1;
or a shift
if(count_val == ((32'b1<<WIDTH)-1) count_pulse = 1'b1;
or in SystemVerilog, a bit fill
if(count_val == '1) count_pulse = 1'b1;
The syntax you have been trying to use WIDTH'b1 should be translated to 3'b1 which is 001. If this is the case, you do not really need the width specifier. The following will do:
if (counter_val == 1)
or to use precise widths:
if (counter_val == { {WIDTH-1{0}}, 1'b1} )
If you meant, 111, the see dave_59's answer.
This is a module for a 8 bit shift register using two 4 bit shift registers. 4 bit register modules works fine. (Just testing this for right shift for the moment)
module shift_reg_8 (Out,In,shift_left,shift_right,s0,s1,enable,clock);
output [7:0] Out;
wire [3:0]Least_Out,Most_Out;
input [7:0] In;
wire [3:0]Least_In,Most_In;
reg temp;
initial
temp = In[4];
assign {Most_In,Least_In} = In;
input shift_left,shift_right,enable,s0,s1,clock;
shift_reg least_sig_reg(Least_Out,Least_In,shift_left,shift_right,s0,s1,enable,clock);
shift_reg most_sig_reg(Most_Out,Most_In,shift_left,shift_right,s0,s1,enable,clock);
assign Out = {Most_Out,Least_Out};
assign Out[3] = temp;
endmodule
Here's the test bench.
module stimulus;
reg [7:0]INPUT;
reg ENABLE,CLOCK,S0,S1,SL,SR;
wire [7:0] OUTPUT;
shift_reg_8 my8shiftreg(OUTPUT,INPUT,SL,SR,S0,S1,ENABLE,CLOCK); // SL = Shift_Left, SR = Shift_Right, SO,S1 = Controls
initial
begin
CLOCK = 1'b0;
INPUT = 8'b01101110; ENABLE = 1;S0 = 0;S1 = 1;SL = 0;SR = 1;
#14 $display("Test 1 (Right Shift): INPUT = %b, S1 = %b, S0 = %b, SR = %b, OUTPUT = %b\n",INPUT,S1,S0,SR,OUTPUT);
end
always
#5 CLOCK = ~CLOCK;
initial
#100 $stop;
endmodule
This gives an output like this when simulated.
Test 1 (Right Shift): INPUT = 01101110, S1 = 1, S0 = 0, SR = 1, OUTPUT = 1011x111
what might be the problem?
Here's the shift_reg code...
module shift_reg(Out,In,shift_left,shift_right,s0,s1,enable,clock);
output [3:0] Out;
input [3:0] In;
input shift_left,shift_right,enable,s0,s1,clock;
reg [3:0] out_reg;
always #(posedge clock & enable)
begin
if ((s0 == 1'b0) && (s1 == 1'b0)) // Holding
begin
end
else if ((s0 == 1'b1) && (s1 == 1'b0)) // Left Shift
begin
out_reg[0] <= shift_left;
out_reg[1] <= In[0];
out_reg[2] <= In[1];
out_reg[3] <= In[2];
end
else if ((s0 == 1'b0) && (s1 == 1'b1)) // Right Shift
begin
out_reg[0] <= In[1];
out_reg[1] <= In[2];
out_reg[2] <= In[3];
out_reg[3] <= shift_right;
end
else if ((s0 == 1'b1) && (s1 == 1'b1)) // Loading
begin
out_reg <= In;
end
end
assign Out = out_reg;
endmodule
You are assigning out[3] twice.
assign Out = {Most_Out,Least_Out}; // Assigns all 8 bits
assign Out[3] = temp; // Assigns bit 3 again.
The multiple drivers is causing an unknown state.
I am currently programming a blackjack game in verilog with several modules including game logic and scoring. The goal of my project is to display onto a screen through VGA and a nexys3 FPGA board the blackjack game. Before I mess with setting up VGA, I need to make sure that my game logic is correctly working and setting the player hand and player score correctly. Unfortunately the player's hand is not being set correctly and is displaying X values where 1s should be. Below are all of my modules and code and at the bottom is the simulation I am running:
This is the main module that calls my other modules.
module blackJack(
input clk,
input btnhit, //deal card to player
input btnpass, //stay for player/pass to dealer
input btnreset, //reset game to 0 and redeal
output Hsync,
output Vsync,
output reg [2:0] vgaRed,
output reg [2:0] vgaGreen,
output reg [1:0] vgaBlue
);
wire [7:0] plscore;
wire [7:0] dlscore;
wire [7:0] plhand;
wire [7:0] dlhand;
wire [2:0] state;
wire [7:0] plcard;
wire [7:0] dlcard;
wire plbust;
wire dlbust;
wire plbj;
wire dlbj;
wire plhit;
wire dlhit;
wire plwin;
wire pllose;
reg vgaclk;
wire trigger;
clock vclk(
.clk(clk),
.vgaclk(vgaclk)
);
wire hit;
debouncer hitD(
.clk(clk),
.button_in(btnhit),
.button_out(hit)
);
wire pass;
debouncer passD(
.clk(clk),
.button_in(btnpass),
.button_out(pass)
);
wire reset;
debouncer resetD(
.clk(clk),
.button_in(btnreset),
.button_out(reset)
);
controller cntrl(
.clk(clk),
.trigger(trigger),
.state(state),
.curPlHand(plhand),
.curDlHand(dlhand),
.dlhit(dlhit),
.plhit(plhit),
.plwin(plwin),
.pllose(pllose),
.plscore(plscore),
.dlscore(dlscore)
);
randomGen gen(
.clk(clk),
.card1(plcard),
.card2(dlcard)
);
player pl(
.clk(clk),
.addCard(plhit),
.card(plcard),
.hand(plhand)
);
player dl(
.clk(clk),
.addCard(dlhit),
.card(dlcard),
.hand(dlhand)
);
checkBust chkpl(
.clk(clk),
.handTotal(plhand),
.bust(plbust),
.blackJack(plbj)
);
checkBust chkdl(
.clk(clk),
.handTotal(dlhand),
.bust(dlbust),
.blackJack(dlbj)
);
stateMonitor sm(
.clk(clk),
.reset(reset),
.hit(hit),
.pass(pass),
.plwin(plwin),
.pllose(pllose),
.state(state),
.trigger(trigger)
);
endmodule
Here are each individual module.
module clock(
input clk,
output vgaclk
);
reg vgaclk;
reg [31:0] out = 0;
always # (posedge clk) begin
if (out >= 3) begin
out <= 0;
end
if (out == 3) begin
vgaclk <= 1;
end
else begin
vgaclk <= 0;
end
out <= out + 1;
end
endmodule
player module:
module player(
input clk,
input addCard,
input [7:0] card,
output [7:0] hand
);
reg [7:0] hand = 0;
always #(posedge clk) begin
if (addCard == 1)
hand <= hand + card;
end
endmodule
statemonitor module:
module stateMonitor(
input clk,
input reset,
input hit,
input pass,
input plwin,
input pllose,
output [2:0] state,
output trigger
);
reg [2:0] currentState = 3'b000;
reg action = 1;
//modes
//000 = start of game. score = 0 and no hand dealt
//001 = player dealt first card
//010 = player dealt second card
//011 = dealer dealt first card - wait for player to hit or pass
//100 = player hits
//101 = player passes -> dealer hits
//110 = payer wins
//111 = player loses
always # (posedge clk) begin
if (currentState == 3'b000 && action == 0) begin
currentState <= 3'b001;
action <= 1;
end
else if (currentState == 2'b001 && action == 0) begin
currentState <= 3'b010;
action <= 1;
end
else if (currentState == 3'b010 && action == 0) begin
currentState <= 3'b011;
action <= 1;
end
else if (currentState == 3'b011 && action == 0) begin
if (plwin == 1) begin
currentState <= 3'b110;
action <= 1;
end
else if (hit == 1) begin
currentState <= 3'b100;
action <= 1;
end
else if (pass == 1) begin
currentState <= 3'b101;
action <= 1;
end
else if (reset == 1) begin
currentState <= 3'b000;
action <= 1;
end
end
else if (currentState == 3'b100 && action == 0) begin
if (plwin == 1) begin
currentState <= 3'b110;
action <= 1;
end
else if (pllose == 1) begin
currentState <= 3'b111;
action <= 1;
end
else if (hit == 1) begin
currentState <= 3'b100;
action <= 1;
end
else if (pass == 1) begin
currentState <= 3'b101;
action <= 1;
end
else if (reset == 1) begin
currentState <= 3'b000;
action <= 1;
end
end
else if (currentState == 3'b101 && action == 0) begin
if (plwin == 1) begin
currentState <= 3'b110;
action <= 1;
end
else if (pllose == 1) begin
currentState <= 3'b111;
action <= 1;
end
else if (reset == 1) begin
currentState <= 3'b000;
action <= 1;
end
else
action <= 1;
end
else if (currentState == 3'b110 && action == 0) begin
if (hit == 1)
currentState <= 3'b000;
end
else if (currentState == 3'b111 && action == 0) begin
if (hit == 1)
currentState <= 3'b000;
end
else
action <= 0;
end
assign state = currentState;
assign trigger = action;
endmodule
controller module:
module controller(
input clk,
input trigger,
input reset,
input plbust,
input dlbust,
input plbj,
input [2:0] state,
output [7:0] curPlHand,
output [7:0] curDlHand,
output dlhit,
output plhit,
output plwin,
output pllose,
output [7:0] plscore,
output [7:0] dlscore
);
reg [7:0] curPlHand;
reg [7:0] curDlHand;
reg [7:0] plscore;
reg [7:0] dlscore;
//reg plbust;
//reg dlbust;
//reg plscore;
//reg dlscore;
reg plhit = 0;
reg dlhit = 0;
reg plwin = 0;
reg pllose = 0;
//modes
//000 = start of game. score = 0 and no hand dealt
//001 = player dealt first card
//010 = player dealt second card
//011 = dealer dealt first card - wait for player to hit or pass
//100 = player hits
//101 = player passes -> dealer hits
//110 = payer wins
//111 = player loses
always #(*) begin
if (plbust == 1)
pllose <= 1;
else if (plbj == 1)
plwin <= 1;
else if (dlbust == 1)
plwin <= 1;
end
always #(posedge clk) begin
plhit <= 0;
dlhit <= 0;
if (state == 3'b000 && trigger) begin
curPlHand <= 8'b00000000;
curDlHand <= 8'b00000000;
if (reset == 1) begin
plscore <= 8'b00000000;
dlscore <= 8'b00000000;
end
end
else if (state == 3'b001 && trigger) begin
plhit <= 1;
end
else if (state == 3'b010 && trigger) begin
plhit <= 1;
end
else if (state == 3'b011 && trigger) begin
if (plbj == 1)
plwin <= 1;
else
dlhit <= 1;
end
else if (state == 3'b100 && trigger) begin
if (plbust == 1)
pllose <= 1;
else if (plbj == 1)
plwin <= 1;
else
plhit <= 1;
end
else if (state == 3'b101 && trigger) begin
if (dlbust == 1)
plwin <= 1;
else if (plbust == 1)
pllose <= 1;
else if (plbj == 1)
plwin <= 1;
else
dlhit <= 1;
end
/*else if (state == 3'b110) begin
end
else if (state == 3'b111) begin
end
*/
end
endmodule
random card generator module:
module randomGen (
input clk,
output card1,
output card2
);
reg [7:0] card1;
reg [7:0] card2;
always # (posedge clk) begin
card1 <= ({$random} % 51 >> 2) + 1;
card2 <= ({$random} % 51 >> 2) + 1;
end
endmodule
check for blackjack and bust module:
module checkBust (
input clk,
input handTotal,
output bust,
output blackJack
);
wire [7:0] handTotal;
reg blackJack;
reg bust;
always #(posedge clk) begin
if(handTotal == 8'd21) begin
bust <= 0;
blackJack <= 1;
end
else if(handTotal > 8'd21) begin
bust <= 1;
blackJack <= 0;
end
else begin
bust <= 0;
blackJack <= 0;
end
end
endmodule
debouncer for FPGA button presses:
module debouncer(
input clk,
input button_in,
output button_out
);
reg [1:0] button_buffer;
assign button_out = button_buffer[0];
always #(posedge clk or posedge button_in) begin
if (button_in)
button_buffer <= 2'b11;
else
button_buffer <= {1'b0, button_buffer[1]};
end
endmodule
Here is the testbench I am currently running:
module testBlackjack;
// Inputs
reg clk;
reg btnhit;
reg btnpass;
reg btnreset;
// Instantiate the Unit Under Test (UUT)
blackJack uut (
.clk(clk),
.btnhit(btnhit),
.btnpass(btnpass),
.btnreset(btnreset)
);
initial begin
// Initialize Inputs
clk = 0;
btnhit = 0;
btnpass = 0;
btnreset = 0;
// Wait 100 ns for global reset to finish
#1000;
$finish;
end
always #20 clk = ~clk;
endmodule
Here is a image of my simulation which is only testing the initial setup of the game by distributing 2 cards to the player and 1 card to the dealer:
As you can see from the simulation, the card 6 is being added to the players hand when plhit = 1 (this is addcard inside the player module). The correct value that should be displayed in plhand should be 00000110 but instead the 1's are X's.
The issue I am having is that when I am attempting to add a card to a player's total hand score (in 8 bits) the bits that should be a 1 are being set as X. I have tried restating plscore as a reg and tried multiple assigning operations however I have no luck. Any help would be greatly appreciated and if there is any information need I will be happy to respond quickly.
A couple if issue:
Fist off the header. You are mixing ANSI and non-ANSI header styles. This is illegal syntax. Some simulator/synthesizer is allowing it, but it is bad practice. I've already answered header related question in more depth here "object <name> is not declared in verlog" and "Issue with parameters in Modelsim" so I'll just summarize; follow ANSI or non-ANSI, don't blend header styles in the same module. You may use different header styles with different modules, but it is recommended to be consistent. I prefer ANSI style.
For example:
module clock(
input clk,
output vgaclk
);
reg vgaclk; // <-- this is mixing styles
...
module checkBust (
input clk,
input handTotal,
output bust,
output blackJack
);
wire [7:0] handTotal; // <-- these are mixing styles too
reg blackJack;
reg bust;
...
should be:
module clock(
input clk, reset,
output reg vgaclk
);
...
module checkBust (
input clk,
input [7:0] handTotal,
output reg bust,
output reg blackJack
);
...
Some signals (for example vgaclk) are not initialized. You could initialize them inline or an initial block, however it is recommended to reset them in an always block. This way you can restore the initial values without powering down the design. FPGAs have limited number of asynchronous reset flops, so use synchronous reset only. ASIC prefer using asynchronous reset flops to initialize all values and use synchronous reset for dynamic resets. Example:
always #(posedge clk) begin
if (reset) begin
hand <= 8'h0;
end
if (addCard == 1) begin
hand <= hand + card;
end
end
plhand and dlhand are begin driven by controller by player. Based on the code, it should only be assigned within player. controller should send a reset signal to player to set the value back to 0.
The last issue I can quickly spot is that following code is infers level-sensitive latches and assigned in two separate always blocks. Latches are not necessarily bad, but they have a higher change of glitching and should only be used when specifically requited. The fact the variables are assigned in two different always blocks will be a synthesis error. I believe you can safely delete the latching code.
always #(*) begin
if (plbust == 1)
pllose <= 1;
else if (plbj == 1)
plwin <= 1;
else if (dlbust == 1)
plwin <= 1;
end
You have to remember that signals in verilog represent physical circuitry. We refer to something that sets a value to a wire signal as a driver. Signals aren't allowed to have multiple drivers, as this can cause shorts (one driver want to put Vdd on a wire, while another connects it to ground).
In your case, both the controller and the player specify that they output to plhand, which makes both of them drivers. So when player want to write a 1 to a bit of plhand, the controller is still writing a 0, which causes a conflict. You should've gotten an error or warning that a signal had multiple drivers, which would let you know that you were getting this behavior.
In short, you can pass a wire between as many modules as you want, but only one of those modules can output to it. So, consider changing curPlHand from an output to an input.
NOTE: This is not the problem. See other answers/comments for more information.
In the player module, you don't set hand properly for all conditions. Specifically:
always #(posedge clk) begin
if (addCard == 1)
hand <= hand + card;
end
needs to handle addCard != 1. So try:
always #(posedge clk) begin
if (addCard == 1)
hand <= hand + card;
else
hand <= hand;
end
Ok so I know my code works for a 3 number sequence but for with the finite state machine model I drew out this should be correct but it doesn't work for a 4 number sequence. It only detects the first 3. I need to detect with an overlap "0110" from the sequence 01100110110111. It should have 3 "0110" sequences and 2 overlapping but when I run my Verilog it detects 4 "0110" sequences which tells me it's only grabbing "011" Can someone look at my code and see what I'm doing wrong? I could simply add another state but I wouldn't think that's the correct way since I don't have another state in my diagram.
module moore_seq
(
input clock, reset, x,
output reg z
);
//assign binary encoded codes to the states A through D
parameter A = 2'b00,
B = 2'b01,
C = 2'b10,
D = 2'b11;
reg [1:0] current_state, next_state;
//Section 1: Next state generator (NSG)
always#(*)
begin
casex(current_state) //ignore unknown and Hi-Z inputs
A: if (x == 1)
next_state = A;
else
next_state = B;
B: if (x == 1)
next_state = C;
else
next_state = B;
C: if (x == 1)
next_state = D;
else
next_state = B;
D: if (x == 1)
next_state = A;
else
next_state = B;
endcase
end
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == D)
z = 1;
else
z = 0;
end
//Section 3: The Flip Flops
always#(posedge clock, posedge reset)
begin
if(reset == 1)
current_state <= A;
else
current_state <= next_state;
end
endmodule
UPDATED:
parameter A = 3'b000,
B = 3'b001,
C = 3'b010,
D = 3'b011,
E = 3'b100;
reg [1:0] current_state, next_state;
//Section 1: Next state generator (NSG)
always#(*)
begin
casex(current_state) //ignore unknown and Hi-Z inputs
A: if (x == 1)
next_state = A;
else
next_state = B;
B: if (x == 1)
next_state = C;
else
next_state = B;
C: if (x == 1)
next_state = D;
else
next_state = B;
D: if (x == 1)
next_state = A;
else
next_state = E;
E: if (x == 1)
next_state = C;
else
next_state = B;
endcase
end
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == E)
z = 1;
else
z = 0;
end
I suppose, four states is enough. Just change
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == D)
to
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == D && x == 0 )