Ok so I know my code works for a 3 number sequence but for with the finite state machine model I drew out this should be correct but it doesn't work for a 4 number sequence. It only detects the first 3. I need to detect with an overlap "0110" from the sequence 01100110110111. It should have 3 "0110" sequences and 2 overlapping but when I run my Verilog it detects 4 "0110" sequences which tells me it's only grabbing "011" Can someone look at my code and see what I'm doing wrong? I could simply add another state but I wouldn't think that's the correct way since I don't have another state in my diagram.
module moore_seq
(
input clock, reset, x,
output reg z
);
//assign binary encoded codes to the states A through D
parameter A = 2'b00,
B = 2'b01,
C = 2'b10,
D = 2'b11;
reg [1:0] current_state, next_state;
//Section 1: Next state generator (NSG)
always#(*)
begin
casex(current_state) //ignore unknown and Hi-Z inputs
A: if (x == 1)
next_state = A;
else
next_state = B;
B: if (x == 1)
next_state = C;
else
next_state = B;
C: if (x == 1)
next_state = D;
else
next_state = B;
D: if (x == 1)
next_state = A;
else
next_state = B;
endcase
end
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == D)
z = 1;
else
z = 0;
end
//Section 3: The Flip Flops
always#(posedge clock, posedge reset)
begin
if(reset == 1)
current_state <= A;
else
current_state <= next_state;
end
endmodule
UPDATED:
parameter A = 3'b000,
B = 3'b001,
C = 3'b010,
D = 3'b011,
E = 3'b100;
reg [1:0] current_state, next_state;
//Section 1: Next state generator (NSG)
always#(*)
begin
casex(current_state) //ignore unknown and Hi-Z inputs
A: if (x == 1)
next_state = A;
else
next_state = B;
B: if (x == 1)
next_state = C;
else
next_state = B;
C: if (x == 1)
next_state = D;
else
next_state = B;
D: if (x == 1)
next_state = A;
else
next_state = E;
E: if (x == 1)
next_state = C;
else
next_state = B;
endcase
end
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == E)
z = 1;
else
z = 0;
end
I suppose, four states is enough. Just change
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == D)
to
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == D && x == 0 )
Related
I have been trying to make an asynchronous fifo in verilog but I'm facing a problem of object "empty" and "full" on left side of assignment should have variable data type.
Top module:
module async_fifo (reset, wclock, rclock, datain, dataout, e, f);
input [15:0] datain;
output reg [15:0] dataout;
//reg [15:0] mem1, mem2, mem3, mem4, mem5, mem6, mem7, mem8;
reg [15:0] mem [7:0];
input reset, rclock, wclock;
/*reg [0:2] wptr, rptr;
initial wptr = 3'b000;
initial rptr = 3'b000;*/
integer wflag = 0, rflag = 0;
wire empty , full;
input e,f;
reg [0:2] wptr = 3'b000, rptr = 3'b000;
counter c(wclock, rclock, empty, full);
e = empty;
f = full;
always#(posedge wclock)
begin
if(f == 1'b0)
begin
e = 1'b0;
if (wptr < 3'b111)
begin
mem[wptr] = datain;
wptr = wptr + 3'b001;
end
else if(wptr == 3'b111 && wflag == 0)
wflag = 1;
else if (wflag == 1)
begin
wptr = 3'b000;
wflag = 0;
end
end
end
always#(posedge rclock)
begin
if(e == 1'b0)
begin
f = 1'b0;
if (rptr < 3'b111)
begin
dataout = mem[rptr];
rptr = rptr + 3'b001;
end
else if(rptr == 3'b111 && rflag == 0)
rflag = 1;
else if (rflag == 1)
begin
rptr = 3'b000;
rflag = 0;
end
end
end
endmodule
Counter module:
module counter(w_clock, r_clock, empty, full);
input w_clock, r_clock;
output reg empty = 0, full = 0;
integer rear = 0, front = 0;
always # (posedge w_clock)
begin
if ((front == 1 && rear == 8) || front == rear + 1)
full = 1;
else if(rear == 8)
begin
rear = 1;
empty = 0;
end
else
begin
rear = rear+1;
empty = 0;
end
end
always # (posedge r_clock)
begin
if (front == 0 && rear == 0)
empty = 1;
else if(front == 8)
begin
front = 1;
full = 0;
end
else
begin
front = front+1;
full = 0;
end
end
endmodule
You are using full and empty in left hand side of behavioral block (always). So they have to be registers.
But at the same time they are output of counter and have to be wires.
You can't use variables in that way.They can either be output of an instant and only used in right hand side of other parts of code or be regsietrs for using in left hand side of behavioral blocks that can also be input of another instant.
You better change your coding style.
Here is an examole of async FIFO:
http://www.asic-world.com/code/hdl_models/aFifo.v
And also you need to study about blocking & nonblocking assignment and race conditions. Take a look at this:
http://ee.hawaii.edu/~sasaki/EE361/Fall01/vstyle.txt
I am working on designing a finite state machine in Verilog to represent a stack. The module is as follows:
module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output reg OF_Err = 0, UF_Err = 0;
reg [2:0] y, Y;
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
always #(s, y, Enable)
if (Enable)
begin
case (y)
A: if (s == 3'b000) Y = B;
else
begin
Y = A;
UF_Err = 1;
end
B: if (s == 3'b000) Y = C;
else if (s == 3'b001) Y = A;
else
begin
Y = B;
UF_Err = 1;
end
C: if (s == 3'b000) Y = D;
else if (s == 3'b100) Y = C;
else Y = B;
D: if (s == 3'b000) Y = E;
else if (s == 3'b100) Y = D;
else Y = C;
E: if (s == 3'b000)
begin
Y = E;
OF_Err = 1;
end
else if (s == 3'b100) Y = E;
else Y = D;
default: Y = 3'bxxx;
endcase
c[1] = y[1];
c[0] = y[0];
end
always #(negedge Resetn, posedge Clock)
begin
if (Resetn == 0)
begin
y <= A;
OF_Err = 0; //Problem
UF_Err = 0; //Problem
end
else y <= Y;
end
OF_Err and UF_Err are indicators of overflow and underflow errors, respectively.
However, I get the following errors when compiling my project:
Error (10028): Can't resolve multiple constant drivers for net "OF_Err" at state_machine.v(59)
Error (10029): Constant driver at state_machine.v(10)
Error (10028): Can't resolve multiple constant drivers for net "UF_Err" at state_machine.v(59)
These only appeared after I added the commented lines. I want to reset the over- and underflow indicators when the FSM is reset, but I can't do it the way I have it. How do I go about doing this?
(If it's of any value, this is to be executed on an Altera DE2-115).
In two always blocks you have assigned the values to OF_Err and UF_Err. This is the reason it is showing multiple constant driver error.
module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output OF_Err, UF_Err; //modified
reg [2:0] y, Y;
reg of_Err, uf_Err; //added
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E =3'b100;
always #*
begin
if (Enable)
begin
case (y)
A: if (s == 3'b000)
Y = B;
else
begin
Y = A;
uf_Err = 1; //modified
end
B: if (s == 3'b000)
Y = C;
else if (s == 3'b001)
Y = A;
else
begin
Y = B;
uf_Err = 1; //modified
end
C: if (s == 3'b000)
Y = D;
else if (s == 3'b100)
Y = C;
else
Y = B;
D: if (s == 3'b000)
Y = E;
else if (s == 3'b100)
Y = D;
else Y = C;
E: if (s == 3'b000)
begin
Y = E;
of_Err = 1; //modified
end
else if (s == 3'b100) Y = E;
else Y = D;
default: Y = 3'bxxx;
endcase
c[1] = y[1];
c[0] = y[0];
end
else
begin
//write the condition if the Enable signal is not high.I guess you're trying to synthesize
end
end
always #(negedge Resetn, posedge Clock)
begin
if (Resetn == 0)
begin
y <= A;
// OF_Err = 0; //Problem
// UF_Err = 0; //Problem
end
else y <= Y;
end
assign OF_Err = !Resetn? of_Err : 1'b0; //added
assign UF_Err = !Resetn? uf_Err : 1'b0; //added
endmodule
As others have already pointed out, OF_Err and UF_Err were driver by two always blocks which is illegal for synthesis. I recommend creating two additional variables of_Err and uf_Err like Arvind suggested. However I recommend keeping OF_Err and UF_Err as flops.
The if (Enable) in the combinational block infers Y,c and the *_Err as level-sensitive latches. I highly doubt this is what you intendeds. I recommend moving the if (Enable) into synchronous always block and keeping the combinational logic as pure combinational.
c is a simple assignment, so it might make more sense having it as a wire instead of a reg with a simple assign statement. It can be in the combinational block, but I prefer to separate combinational input from output.
You did use #(s, y, Enable) correctly, however #* or the synonymous #(*) is recommenced for combinational block. #* is an auto sensitivity list which saves you typing, maintenance, and removes the risk of forgetting a signal.
always #*
begin
of_Err = OF_Err; // <-- default values
uf_Err = UF_Err;
case (y)
// ... your original case code with OF_Err/UF_Err renamed to of_Err/uf_Err
endcase
end
always #(posedge Clock, negedge Resetn) // style difference, I prefer the clock to be first
begin
if (Resetn == 1'b0)
begin
y <= A;
OF_Err <= 1'b0;
UF_Err <= 1'b0;
end
else if (Enable)
begin
y <= Y;
OF_Err <= of_Err;
UF_Err <= uf_Err;
end
end
assign c[1:0] = y[1:0];
Because OF_Err and UF_ERR are driven by multiple always blocks.
A reg should be driven by only one always block. And if it is having
multiple drivers by design, then it should be a wire.
Here is your modified code.
module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output reg OF_Err = 0, UF_Err = 0;
reg [2:0] y, Y;
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
always #(s, y, Enable, negedge reset)
begin
if (!reset)
begin
OF_Err = 0; //Problem
UF_Err = 0; //Problem
end
else
begin
if (Enable)
begin
case (y)
A: if (s == 3'b000) Y = B;
else
begin
Y = A;
UF_Err = 1;
end
B: if (s == 3'b000) Y = C;
else if (s == 3'b001) Y = A;
else
begin
Y = B;
UF_Err = 1;
end
C: if (s == 3'b000) Y = D;
else if (s == 3'b100) Y = C;
else Y = B;
D: if (s == 3'b000) Y = E;
else if (s == 3'b100) Y = D;
else Y = C;
E: if (s == 3'b000)
begin
Y = E;
OF_Err = 1;
end
else if (s == 3'b100) Y = E;
else Y = D;
default: Y = 3'bxxx;
endcase
c[1] = y[1];
c[0] = y[0];
end
end
end
always #(negedge Resetn, posedge Clock)
begin
if(Resetn == 0)
y <= A;
else
y <= Y;
end
This is a module for a 8 bit shift register using two 4 bit shift registers. 4 bit register modules works fine. (Just testing this for right shift for the moment)
module shift_reg_8 (Out,In,shift_left,shift_right,s0,s1,enable,clock);
output [7:0] Out;
wire [3:0]Least_Out,Most_Out;
input [7:0] In;
wire [3:0]Least_In,Most_In;
reg temp;
initial
temp = In[4];
assign {Most_In,Least_In} = In;
input shift_left,shift_right,enable,s0,s1,clock;
shift_reg least_sig_reg(Least_Out,Least_In,shift_left,shift_right,s0,s1,enable,clock);
shift_reg most_sig_reg(Most_Out,Most_In,shift_left,shift_right,s0,s1,enable,clock);
assign Out = {Most_Out,Least_Out};
assign Out[3] = temp;
endmodule
Here's the test bench.
module stimulus;
reg [7:0]INPUT;
reg ENABLE,CLOCK,S0,S1,SL,SR;
wire [7:0] OUTPUT;
shift_reg_8 my8shiftreg(OUTPUT,INPUT,SL,SR,S0,S1,ENABLE,CLOCK); // SL = Shift_Left, SR = Shift_Right, SO,S1 = Controls
initial
begin
CLOCK = 1'b0;
INPUT = 8'b01101110; ENABLE = 1;S0 = 0;S1 = 1;SL = 0;SR = 1;
#14 $display("Test 1 (Right Shift): INPUT = %b, S1 = %b, S0 = %b, SR = %b, OUTPUT = %b\n",INPUT,S1,S0,SR,OUTPUT);
end
always
#5 CLOCK = ~CLOCK;
initial
#100 $stop;
endmodule
This gives an output like this when simulated.
Test 1 (Right Shift): INPUT = 01101110, S1 = 1, S0 = 0, SR = 1, OUTPUT = 1011x111
what might be the problem?
Here's the shift_reg code...
module shift_reg(Out,In,shift_left,shift_right,s0,s1,enable,clock);
output [3:0] Out;
input [3:0] In;
input shift_left,shift_right,enable,s0,s1,clock;
reg [3:0] out_reg;
always #(posedge clock & enable)
begin
if ((s0 == 1'b0) && (s1 == 1'b0)) // Holding
begin
end
else if ((s0 == 1'b1) && (s1 == 1'b0)) // Left Shift
begin
out_reg[0] <= shift_left;
out_reg[1] <= In[0];
out_reg[2] <= In[1];
out_reg[3] <= In[2];
end
else if ((s0 == 1'b0) && (s1 == 1'b1)) // Right Shift
begin
out_reg[0] <= In[1];
out_reg[1] <= In[2];
out_reg[2] <= In[3];
out_reg[3] <= shift_right;
end
else if ((s0 == 1'b1) && (s1 == 1'b1)) // Loading
begin
out_reg <= In;
end
end
assign Out = out_reg;
endmodule
You are assigning out[3] twice.
assign Out = {Most_Out,Least_Out}; // Assigns all 8 bits
assign Out[3] = temp; // Assigns bit 3 again.
The multiple drivers is causing an unknown state.
I'm checking primality of a number in a form of 6n+1 or 6n-1. I have the below code, but it doesn't seem to be generated correct result.
module prime(clk, rst, start, A, ready, P);
input clk, rst, start;
input [7:0] A;
output ready, P;
reg ready, P;
reg [7:0] divisor;
reg val;
always # (posedge clk or negedge rst) begin
if (!rst) begin
P <= 1'bx;
end
else if (start)
begin
case (A)
-1 : P <= 1;
0 : P <= 1;
1 : P <= 1;
2 : P <= 1;
3 : P <= 1;
5 : P <= 1;
endcase
if (A%2 == 0 && A != 2) begin
P <= 0;
ready <= 1;
end
else if(A > 6)
begin
for(divisor = 5; divisor <= A/divisor; divisor=divisor+6) begin
if (A%divisor == 0 || A%(divisor+2) == 0) begin
P <= 0;
end
end
if (P != 0 && P == 1'bx) begin // need to fix
P <= 1;
end
end
end
end
endmodule
The point is that this part doesn't seem to be working:
if (P != 0 && P == 1'bx)
How can I check whether a variable includes unknown logic, meaning x. Checking as the above
P == 1'bx
doesn't seem to be working.
You should rather use case equality operator (===), which tests 4-state logical equality, then logical equality operator (==).
For the == operator, the result is x, if either operand contains an x or a z.
For the === operator bits with x and z are included in the comparison.
I'm in the process of implementing a finite state machine in verilog, and I've encountered an issue. However, I know what the problem is, but I'm not sure how to fix it.
This is my current code:
module moore_SM(clk, rstn, btn, z, rstLED, state);
//Port Assignments
input clk, rstn;
input [2:0] btn;
output z;
output reg rstLED;
output reg [5:0] state;
//Internal Port Assignments
reg [1:0] w, x; //NOTE: This is typically the input in FSM,
//but it is internal because there is a conversion from btn to w.
reg [2:0] y, Y; //Present state and next state respectively
reg [2:0] pstBtn;
reg [31:0] cnt;
//Define some parameters
//Input Type (i.e. A, B or C)
parameter [1:0] A = 2'b00, B = 2'b01, C = 2'b11, DC = 2'b10; //DC => don't care - shouldn't affect FSM
//State (i.e. S1, S2, S3, S4, S5 or S6)
parameter [2:0] S1 = 3'b000, S2 = 3'b001, S3 = 3'b010, S4 = 3'b011, S5 = 3'b100, S6 = 3'b101;
initial begin
state = 0;
end
//Determine which button is active
always #(*)
begin
case(btn)
3'b110: begin w = A; end
3'b101: begin w = B; end
3'b011: begin w = C; end
// default: w = DC;
endcase
end
//Define the next state and output combinational circuits
always #(w,y)
begin
case(y)
S1: begin
state = 6'b000001;
if(w == A) begin Y = S2; end
else begin Y = S1; end
end
S2: begin
state = 6'b000010;
if(w == B) begin Y = S3; end
else begin if(w == A) begin Y = S2; end
else Y = S1; end
end
S3: begin
state = 6'b000100;
if(w == A) begin Y = S2; end
else begin if(w == B) begin Y = S4; end
else Y = S1; end
end
S4: begin
state = 6'b001000;
if(w == A) begin Y = S5; end
else begin Y = S1; end
end
S5: begin
state = 6'b010000;
if(w == A) begin Y = S2; end
else begin if(w == B) begin Y = S3; end
else Y = S6; end
end
S6: begin
state = 6'b100000;
if(w == A) begin Y = S2; end
else begin Y = S1; end
end
//default: Y = 3'b111;
endcase
end
//assign z = (Y == S2);
//Define the sequential block
always #(posedge clk)
begin
y <= Y;
end
endmodule
This code is supposed to identify the pattern ABBAC. I believe the logic accomplishes this purpose.
However, I've encountered a problem. When I press one of the three buttons, the first always block - always #(*) - executes and evaluates the change. The state of the button is encoded and saved into w. At the same time, the next always block - always #(w,y) - senses a change and determines in which state to reside. Like I expected, if I send input A, the machine moves from S1 into S2.
Now if I send input B, the machine moves back into state S1. After I changed a few things around, I identified what I believe to be the problem. Note the last always block: always #(posedge clk). This always block continuously updates the present state, y. When I press a button, I assume what is happening is that the second always block, always #(w,y), is receiving an updated y at 50mHz (in my case), which is obviously much faster than I can press and release a button. Assuming I'm pressing the B button while in state S2, the state quickly changes to S3 to S4 and then to S1 because of the continuous update.
That said, I'm having some trouble coming up with a way to fix this issue. I basically need some way to change only one state per button press.
Note that I'm primarily testing this code on an experimental board. I did write a testbench, but the simulation does not seem to match what I'm seeing on the design board. In case anyone wants to see the testbench code, I posted it below:
`timescale 1ns/1ns
module moore_SM_TB();
reg clk;
reg [2:0] btn;
wire [5:0] state;
wire z;
wire rstLED;
initial begin
clk = 1;
#0 btn = 3'b111;
#50 btn = 3'b110;
#50 btn = 3'b111;
#50 btn = 3'b101;
#50 btn = 3'b111;
#50 btn = 3'b011;
#50 btn = 3'b111;
end
always begin
#20 clk = ~clk;
end
//MUT
moore_SM MUT (clk, 0, btn, z, rstLED, state);
endmodule
NOTE: I believe the solution will ultimately involve modifying how the buttons are handled. When I release a button, this also registers as a change. Hence, I had to comment out the default case because it would also mess up which state the machine is in.
UPDATE: I wrote a reduced version of the FSM I posted above to try and debug the code. It tries to detect the sequence AB.
module moore_SM(clk, btn, rstN, state, rstLED);
//Port assignments
input clk;
input rstN;
input [2:0] btn;
output reg rstLED;
output reg [5:0] state;
//Internal Port Assignments
reg [1:0] w;
reg [2:0] y, Y;
reg [2:0] pstBtn;
//Define some parameters
parameter [1:0] A = 2'b00, B = 2'b01, C = 2'b11, DC = 2'b10;
parameter [2:0] S1 = 3'b000, S2 = 3'b001, S3 = 3'b010, S4 = 3'b011, S5 = 3'b100, S6 = 3'b101;
//Initialize some values to prevent Quartus from doing
initial
begin
y = S1;
Y = y;
state = 0;
rstLED = 0;
end
always #(*)
begin
if(btn == pstBtn) begin w = DC; end
else begin
case(btn)
3'b110: w = A;
3'b101: w = B;
3'b011: w = C;
default: w = DC;
endcase
end
end
always #(*)
begin
case(y)
S1: begin
state = 6'b000001;
if(w == A) begin Y = S2; end
else begin Y = S1; end
end
S2: begin
state = 6'b000010;
if(w == B) begin Y = S3; end
if(w == DC) begin Y = S2; end
else begin Y = S1; end
end
S3: begin
state = 6'b000100;
if(w == DC) begin Y = S3; end
else begin Y = S1; end
end
default: begin state = 6'b100000; Y = S1; end
endcase
end
//Update state and check for reset signal
always #(posedge clk, negedge rstN)
begin
pstBtn <= btn;
if(rstN == 0) begin y <= S1; rstLED <= 1; end
else begin y <= Y; rstLED <= 0; end
end
endmodule
Note that I'm trying to "sample" the button state in the last always block. I've used this method in the past, but it does not seem to work here. Whenever I press a button, there is no change in state. I'm wondering if this is a timing issue now.
If the button input is coming a switch rather than test stimulus it will be asynchronous and so should be put through 2 meta-stability flip-flops. To change one state per button press create an edge detection.
Edge detection will create a 1 clock period wide pulse, resulting in 1 transition per press.
reg [2:0] btn0_meta;
always #(posedge clk or negedge rstN) begin
if (~rstN) begin
btn0_meta <= 'b0;
end
else begin
btn0_meta <= {btn0_meta[1:0], btn[0]};
end
end
reg btn0_posedge;
always #* begin
btn0_posedge = btn0_meta[1] & ~btn_meta[2];
end
Do this for all button inputs and use the btnX_posedge in your state machine.