I am trying to code and synthesize in Verilog. Sometimes I am still getting confused with using Verilog as a typical C like programming language, I am trying to understand if there will be a difference between 2 different codes:
always # (a1,a0,b1,b0)
begin
case ({a1,a0,b1,b0})
4'b0000 : s= 7'b1110111 ;
4'b0001 : s= 7'b1110111 ;
....
....
4'b1110 : s= 7'b0101111 ;
4'b1111 : s= 7'b1111010 ;
endcase
end
and
using the above code logic with assign, instead of always block.
Will the above code generate a latch? In which case would it generate a latch? Will there be any delay difference between using the 2 codes?
PS we are trying to create a 2bit binary multiplier, which outputs to a 7 segm display.
Thank you.
Latches are generated when one or more paths through a conditional statement are unassigned. For example:
reg [1:0] a;
reg b;
always#(*)
case (a)
0: b=0;
1: b=0;
2: b=1;
endcase
would generate a latch, because I did not cover the a=3 case. You can avoid this by either explicitly covering each case (like it appears you have done) or by using the default case.
For assign statements, it depends on how you format them, but you're significantly less likely to accidentally infer a latch. For example, if you you the ternary operation (i.e. assign b = a? 1:0;) both halves of the if are inferred.
As for delay, case vs. assign should create the same netlist, so they should produce similar or identical results, provided they're logically identical.
(As a side note, it's good practice to use always#(*), rather than always # (a1,a0,b1,b0); The synthesis tool can figure out the correct sensitivity list.)
Related
I have a conditional 2-bit variable coming in. Based off its value, the current value is either incremented or decremented. By that, I mean:
module verilog_block(clk, cond, incr, curr_val)
input clk;
input [1:0] cond;
input [5:0] incr;
output reg [5:0] curr_val;
always # posedge(clk)
begin
curr_val <= curr_val + (!cond[1] - cond[1]) * incr * cond[0];
end
endmodule
Sorry if I made any mistakes, I haven't checked this specific code, as I am just trying to illustrate my question. If cond[0]==0, I don't want curr_val to change (irrespective of cond[1]). If cond[1]==1, I want curr_val to reduce by incr, and if cond[1]==0, I want curr_val to increment by incr.
I think this works, theoretically, but my goal is to expand this into a much larger code. Therefore, it needs to be optimized. I know that the * operator can be slow and require a lot of resources, but I am not sure if that applies to the case of multiplication with only one bit.
If you can spot a way to make this code optimized for area, please let me know. Thanks a lot.
Any good synthesis tool will optimize multiplication where it can, especially when it involves multiplication by zero or any power of 2. But you've created a very hard to read operation. Why not write it the way you said it:
always # posedge(clk)
begin
if (cond[0]==1)
curr_val <= curr_val + (cond[1]==1) ? -incr : incr;
end
Hi I have a simple verilog statements where I want to transfer value at real net to a wire using assign statement. However I see a wire at "x" all the time regardless of the value of a real variable. Here is a snapshot of a sample code with values annotated at time zero:
QN is a wire and real_QN is of type real.
Any ideas why QN is at "x" even though real_QN is at "0" ?
So for reference, the "real" type in not synthesizeable. Only mentioning it because it might be relevant. As such, this solution isn't synthesizeable either. But it should work in simulation. You can not just assign one to the other in this case. But there is a function that will do it for you.
real someReal;
reg [63:1]someReg;
initial begin
someReal = 21.0 ;
$display("someReal---->%f",someReal);
$display("someReg---->%b",someReg);
#1
someReg = $realtobits(someReal);
$display("someReg---->%b",someReg);
Let me know if that does not work for you.
I am trying to debug my code shown below. I am fairly new to SystemVerilog and hopefully I can learn from this. Let me know of any suggestions.
The errors I am receiving are:
Error-[ICPD] Invalid procedural driver combination
"divide.v", 2
Variable "Q" is driven by an invalid combination of procedural drivers.
Variables written on left-hand of "always_comb" cannot be written to by any
other processes, including other "always_comb" processes.
"divide.v", 2: logic [7:0] Q;
"divide.v", 8: always_comb begin
if (x <= R) begin
...
"divide.v", 5: Q = 8'b0;
Error-[ICPD] Invalid procedural driver combination
"divide.v", 2
Variable "R" is driven by an invalid combination of procedural drivers.
Variables written on left-hand of "always_comb" cannot be written to by any
other processes, including other "always_comb" processes.
"divide.v", 2: logic [7:0] R;
"divide.v", 8: always_comb begin
if (x <= R) begin
...
"divide.v",6: R = y;
My SystemVerilog Code is:
module divider(input logic [7:0] x,y,
output logic [7:0] Q,R);
initial
begin
Q = 8'd0;
R = y;
end
always_comb
begin
if (x<=R)
begin R <= R - x; Q <= Q + 8'd1; end
end
endmodule
module test1;
logic [7:0] x,y,Q,R;
divider Divider1 (x,y,Q,R);
initial
begin
x = 8'd2;
y = 8'd8;
end
endmodule
Generally, in Verilog/SystemVerilog you cannot assign to a variable from two parallel blocks (with some exceptions). You are assigning to R and Q from two places: the initial block and the always_comb block.
Although the initial block only runs once, it runs in parallel with the always_comb block at the beginning of the simulation, which is a violation of this rule.
Why don't you get rid of the initial block and do everything in always_comb?
always_comb
begin
Q = 8'd0; // set initial value of Q
R = y; // set initial value of R
.... //THE REST OF THE ALGORITHM
end
Also, you are missing using a loop!
An important distinction between writing System Verilog (or any HDL) and writing in any software language (C/C++, Java, etc) is that System Verilog is designed to facilitate describing hardware structures while allowing for software-like testbenches, while software languages are designed to allow users to give instructions to an interpreter, VM or actual hardware. That being said, you need to think first about the hardware you are trying to describe and then write the associated HDL code. There are numerous posts describing the differences between HDLs and software languages (ex: Can Verilog/Systemverilog/VHDL be considered actor oriented programming languages?).
Looking at your code and flow chart you were given, it appears you are trying to use System Verilog as a programming language rather than a HDL. For example, initial blocks are generally only used in test benches and not in modules themselves. Also, as your algorithm is sequential, it is likely you will need a clock signal and registers, but the way your code lacks both.
Ideally, you should have a good idea of how to design digital hardware systems before trying to code any HDL, as this is the mentality you should have using HDLs. The goal is generally to translate a hardware design into HDL, so understanding digital design will help clarify alot.
I was wondering that if a wire is declared in a Verilog code, but it is not assigned any value, does Verilog treat its value as ZERO ?
For example, I see a code where:
wire start;
module_if my_module_if(.clk(in_clk), .start(start));
Can I assume that the value of "start" will be zero?
Is this an acceptable style for Verilog?
Nets (including wire) without an assignment will be initialized to 'z' (aka high-impedance).
But if you are trying to use "start" as some kind variable or state, then you should probably declare it as "reg" or "logic" (System-Verilog) rather than "wire" (which tends to be used more for interconnect).
Style-wise, it may be less error-prone for you and for the reader of the code to be explicit about the initialization of your logic. For example ...
logic start;
initial begin
start = 1'b0;
end
I'm a bit confused about what is considered an input when you use the wildcard #* in an always block sensitivity list. For instance, in the following example which signals are interpreted as inputs that cause the always block to be reevaluated? From what I understand clk and reset aren't included because they dont appear on the right hand side of any procedural statement in the always block. a and b are included because they both appear on the right hand side of procedural statements in the always block. But where I'm really confused about is en and mux. Because they are used as test conditions in the if and case statements are they considered inputs? Is the always block reevaluated each time en and mux change value? I'm pretty much a noob, and in the 3 Verilog books I have I haven't found a satisfactory explanation. I've always found the explanations here to be really helpful. Thanks
module example
(
input wire clk, reset, en, a, b,
input wire [1:0] mux,
output reg x,y, z
);
always #*
begin
x = a & b;
if (en)
y= a | b;
case(mux)
2'b00: z = 0;
2'b01: z = 1;
2'b10: z = 1;
2'b11: z = 0;
endcase
end
endmodule
Any signal that is read inside a block, and so may cause the result of a block to change if it's value changes, will be included by #*. Any change on a read signal used must cause the block to be re-evaluated, as it could cause the outputs of the block to change. As I'm sure you know, if you hadn't used #* you'd be listing those signals out by hand.
In the case of the code you've provided it's any signal that is:
Evaluated on the right hand side of an assignment (a and b)
Evaluated as part of a conditional (en and mux)
...but it's any signal that would be evaluated for any reason. (I can't think of any other reasons right now, but maybe someone else can)
clk and reset aren't on the sensitivity list because they aren't used. Simple as that. There's nothing special about them; they're signals like any other.
In your example, the following signals are included in the implicit sensitivity list:
a
b
en
mux
clk and reset are not part of the sensitivity list.
This is described completely in the IEEE Std for Verilog (1800-2009, for example). The IEEE spec is the best source of detailed information on Verilog. The documentation for your simulator may also describe how #* works.
The simplest answer depends on if you are writing RTL, or a testbench. If you are writing RTL then you should try to forget about the concept of Sensitivity lists, as they don't really exist. There is no logic that only updates when an item on the list is triggered. All sensitivity lists can do in RTL is cause your simulation and actual circuit to differ, they don't do anything good.
So, always use "always #*" or better yet "always_comb" and forget about the concept of sensitivity lists. If the item in the code is evaluated it will trigger the process. Simple as that. It an item is in an if/else, a case, assigned to a variable, or anything else, it will be "evaluated" and thus cause the process to be triggered.
But, just remember, in digital circuits, there is no sensitivity list.