Structural 2-1 mux fails during elaboration - verilog

Question

So I'm trying to write a simple 2-1 mux in Verilog using logic gates and I'm not sure what I'm doing wrong. The code for the mux is as follows:
module MUX_2_1 (i0 ,i1, sel ,o);
input [31:0] i0, i1;
input sel;
output [31:0] o;
wire [31:0] a, b;
and #(8) and1(a, {32{sel}}, i0);
and #(8) and2(b, {32{~sel}}, i1);
or #(8) or1(o, a, b);
endmodule
The module compiles ok, but when I elaborate my test bench I get several errors (one for each gate) that take the form of
gate (and1) has illegal output specification.
I understand how to make write the same mux using data flow, but I'm curious what the actual problem is here. I can't find anything online that suggests that the above code shouldn't work.
For reference, here is my test bench code:
module test_bench;
reg [31:0] I0, I1, I2, I3, I4, I5, I6, I7;
reg [2:0] SEL;
wire [31:0] O8;
//MUX_8_1 mux(I0, I1, I2, I3, I4, I5, I6, I7, SEL, O8);
MUX_2_1 mux(I0, I1, SEL[0], O8);
initial
begin
I0 = 1;
I1 = 2;
I2 = 4;
I3 = 8;
I4 = 16;
I5 = 32;
I6 = 64;
I7 = 128;
SEL = 3'b000;
#50 $display("SEL = %u, O8 = %u\n", SEL, O8);
SEL = 3'b001;
#50 $display("SEL = %u, O8 = %u\n", SEL, O8);
SEL = 3'b010;
#50 $display("SEL = %u, O8 = %u\n", SEL, O8);
SEL = 3'b011;
#50 $display("SEL = %u, O8 = %u\n", SEL, O8);
SEL = 3'b111;
#50 $display("SEL = %u, O8 = %u\n", SEL, O8);
SEL = 3'b110;
#50 $display("SEL = %u, O8 = %u\n", SEL, O8);
SEL = 3'b100;
#50 $display("SEL = %u, O8 = %u\n", SEL, O8);
SEL = 3'b101;
#50 $display("SEL = %u, O8 = %u\n", SEL, O8);
end
endmodule

Answer 1

What you have done is that you have overridden the parameter of the module (primitive in your case).
To assign the delay of the gate, it is just #<delay_value> used. So you instantiation may look like this:
and #8 and1...;
and #8 and2...;
or #8 or1...;
Paremeter is a very different thing altogether.
A parameter is defined by Verilog as a constant value declared within
the module structure. The value can be used to define a set of
attributes for the module which can characterize its behavior as well
as its physical representation
Suppose you want to make a verilog code, robust for the number of nets or configurable, then you can use the parameters.
For example :
module x (a, b);
input [SIZE-1:0] a;
output [SIZE-1:0] b;
parameter SIZE = 4;
// Your actual Verilog code
endmodule
So this code, by default generate a[3:0], b[3:0]. But since, it is parameterised by the SIZE value. One can override the SIZE value to get different number of nets.
And to override the parameter value, you can use #(<Paramter 1 Value>, <Parameter 2 Value>, ..., <Parameter n Value>).
So if you instantiate module x, with SIZE = 6, then you should write like below:
x x1 #(6) (a, b); // Here SIZE = 6, and so 1[5:0], b[5:0]
Hope you have understood the difference.