I'm not that familiar in Verilog but can you call another module when it's inside a case statement?
You cannot call a module just as you do in C language, since it's not a function, you instantiate it.
If you want to instantiate a module, you should use generate.
Edit: An example of using generate with a case statement can be found here.
2nd edit: If you just wanted to call a section of code in a case-statement then you can create a task or a function. More information here. (credit goes to Hida)
you can not call module within case statement , but you can create function and then call in case statement (task is not synthesizeble)
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For Python 3. I want to call a nested function from a top-level function. NOT access a variable in a nested function but call a nested function (what I'd normally refer to as a subroutine) from a "parent" function.
Answers on SO and elsewhere describe how to use the global and nonlocal keywords to enable variables in nested functions to be accessed by "parent" functions. But I haven't been able to translate that technique to Python 3 nested functions.
What I'm hoping to achieve, largely for outer-to-inner readability, is:
def topLevelFunction(listOfStrings):
# Top-level function's code here.
desiredValue = nestedFunction(dataToModify)
return(desiredResult)
# This nested function's source code is visibly contained within its parent.
def nestedFunction(oneListEntry):
# Modify data passed to function.
return(fixedData)
This structure of course produces UnboundLocalError: local variable 'nestedFunction' referenced before assignment.
I've circumvented that with:
def topLevelFunction(listofStrings):
def nestedFunction(oneListEntry):
# nestedFunction's code goes here.
return(fixedData)
# topLevelFunction's code goes here.
# Only in this "upside down" structure can top-level function call nestedFunction?
return(desiredResult)
Part of the problem seems to be that the nonlocal / global keywords that enable me to reference variables outside of nested functions' scope haven't enabled me to do the same thing for nested functions themselves(?) Or if they do, the syntax is unique? If that's the case, thanks for a pointer to that specific syntax.
I've also made nestedFunction a stand-alone function at the same level / scope as topLevelFunction. But at least from a readability perspective both circumventions (I won't call them fixes) seem to require me to write "upside down" code where things that are used later in the program flow must be "higher" in the source code?
Perhaps I'm too accustomed to compiled languages that don't require this? Or must I instead create a Python 3 class?
I am writing a Python python program that includes two functions: bot.say() and message_sent(). I want message_sent() to be called every time bot.say() is called, in an efficient manner. How would this be achieved?
One simple way would be make a function call both of them, and use that in your code instead of bot.say(). From the two examples you provided, assuming there's nothing else to pass in, you could do something like below.
def bot_message(bot):
bot.say()
message_sent()
In a declarative Microsoft webtest, is there any way to break out of a 'For' loop?
I am using the For loop's PageCounter in my requests and am searching for something in each page response. When I find 'something', I would like to break out of the loop. I'm sure this can easily be done in code, but I would like to stick to just the declarative test script.
This is in reference to a declarative .webtest file in a Visual Studio "Web Performance and Load Test" project.
In a comment you describe the code to be:
Loop (Initialize to 1, Increment by 1, While {{Pagecounter}} < 21) If (The context parameter "SelectedItemBank" does not exist) {{AdminServer}}/item-banks/list.ssp
You might terminate the loop early by writing a suitable value to Pagecounter. It is easy to write a plugin that would set the value based on some test. I am not aware of any built in facilities that will modify the control of the loop.
For one load test I wrote a few simple plugins to do simple arithmetic on context parameter values. These I used to manipulate values to control a loop. For another load test I wrote a web test loop based on a context parameter existence. A plugin set the context parameter when the loop should be terminated.
I have got a piece of verilog code, which i am trying to synthesize. There is a line in there,
MUX2B_XB gas34 ( notPropSig, OECin, generate, notCoutSig );
instantiating a module. Where, the module implements a simple Boolean logic. But, synthesizer was giving an error:
Syntax error near "generate".
I can not understand the use of 'generate' statement in this context here while instantiation and also how to go about resolving the error without affecting the intended functionality.
You seem to be trying to use generate as a variable name and connect that variable to the 3rd port of your module. However, generate is a Verilog keyword and cannot be used as a variable name (another example would be trying to use always as a variable like logic [1:0] always;, you cannot use such keywords as variable names). You simply need to change the name of that variable:
logic gen; // Or whatever the type and width of this line should be
...
MUX2B_XB gas34(notPropSig, OECin, gen, notCoutSig);
If you actually what to use the generate construct for something, you'll need to provide more context so we can help.
It is a macro in the glib.h, but, I am not able to get the function code.
Thanks.
It's a macro, it's not a function and it doesn't have any separate code. The definition is contained entirely in glib.h .
You can see how it's defined, for instance, here: http://library.developer.nokia.com/index.jsp?topic=/S60_3rd_Edition_Cpp_Developers_Library/GUID-759FBC7F-5384-4487-8457-A8D4B76F6AA6/html/gmacros_8h.html