VHDL - library doesn't work - iis

Question

I've create a new project on Quartus II with VHDL, but after I run it give me the errors shown below. Do you have any idea why?
Error (10481): VHDL Use Clause error at test_VHDL.vhd(5): design library "work" does not contain primary unit "std_arith"
Error (10800): VHDL error at test_VHDL.vhd(5): selected name in use clause is not an expanded name
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning
Error: Peak virtual memory: 1003 megabytes
Error: Processing ended: Sat Dec 5 19:50:39 2015
Error: Elapsed time: 00:00:13
Error: Total CPU time (on all processors): 00:00:38
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning
Here is my code:
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.std_arith.all; --extinde operatorul ” + “ la opera]ii \ntre semnale
--[i numere \ntregi
entity SUM is
port (a : in std_logic_vector(3 downto 0);
b : in std_logic;
ini,start,clk,a_disponibil,b_disponibil : in std_logic;
sum : out std_logic_vector(4 downto 0);
q : inout std_logic_vector(4 downto 0));
end SUM;
architecture arch_SUM of SUM is
signal load_a,load_b,reset,load_s : std_logic;
signal z : std_logic_vector(0 to 3);
type STARE is (S0,S1,S2,S3,S4); --st`rile automatului
signal S : STARE;
begin
--NUMARATOR
---------------------------------------------------------------
NUM : process(b)
begin
if rising_edge(b) then
if reset='1' then q<=(others=>'0');
elsif load_a='1' then
for i in 3 downto 0 loop --\ncarc` operandul a
q(i) <= a(i); --\n ultimii 3 bistabili
end loop; --ai num`r`torului
elsif load_b='1' then
q <= q+1; --adun` b la a
end if;
end if;
end process NUM;
--REGISTRU
--------------------------------------------------------------------
REG: process(clk)
begin
if rising_edge(clk) then
if reset='1' then sum<=(others=>'0');
elsif load_s='1' then
sum<=q;
end if;
end if;
end process REG;
--AUTOMAT
-----------------------------------------------------------------------------------
AUTOMAT : process(ini,clk)
begin
if INI='1' then s<=S0; --ini]ializeaz` automatul
elsif rising_edge(clk) then
case S is --descrie diagrama st`rilor
when S0 =>
if start='1' then S<=S1;
else S<=S0;
end if;
when S1 =>
if a_disponibil='1' then S<=S2;
else S<=S1;
end if;
when S2 =>
if b_disponibil='1' then S<=S3;
else S<=S2;
end if;
when S3 =>
if b_disponibil='0' then S<=S4;
else S<=S3;
end if;
when S4 => S<=S0;
end case;
end if;
end process AUTOMAT;
with S select
z<= "0000" when S0, --genereaz` ie[irea
"0010" when S1,
"1000" when S2,
"0100" when S3,
"0001" when others;
load_a <= z(0);
load_b <= z(1); --conexiuni interne
reset <= z(2);
load_s <= z(3);
end arch_SUM;
Have anyone idea why and how can solve it?

Answer 1

The statement use work.std_arith.all; introduces the sysnthesis compiler to look for a package std_arith in the same library as of the VHDL file. If you didn't specify one in the Quartus project settings, that it will be the default library. In this case, you have to provide your own implementation of the package and to add this file to the Quartus project as well.
If you are looking for the non-standard package from Synopsys, then you must change the line to use ieee.std_logic_arith.all;. But, this library does not define an operator + for the type std_logic_vector. EDIT The required operator is defined in the package std_logic_unsigned, if you want to treat your std_logic_vectors as unsigned numbers. The package is included with use ieee.std_logic_unsigned.all;. If you want signed arithmetic instead, then include use ieee.std_logic_signed.all;.
But, I recommend to use the standard IEEE library ieee.numeric_std instead, which defines arithmetic operators on the vector-types unsigned and signed.
For example, declare in the entity
sum : out unsigned(4 downto 0);
q : inout unsigned(4 downto 0);