I am having trouble making testbenches. It is far into the quarter in my school but I feel like I am missing out on some fundamentals.
Here I am trying to make a 2 by 4 decoder, but I want to simulate it inside verilog.
module decoder2to4(x, enable, y);
input [1:0] x; //this is my decoder input
input enable;
output [3:0] y;
reg [3:0] y;
always #(x, enable ) //
begin
if(enable==0) //if enable isn't on, all outputs WON'T OUTPUT correct and give us 1111
y = 4'b1111;
else //if enable is high...
if (x == 2'b00) //...then we check our inputs and give corresponding outputs
y = 4'b0001;
if (x == 2'b01)
y = 4'b0010;
if (x == 2'b10)
y = 4'b0100;
if (x == 2'b11);
y = 4'b1000;
end
endmodule
This is my simulation file ~ did i write it correctly ?
module testbench_2to4decoder;
reg [1:0] x; //use reg not wire to assign values
wire [3:0] y; //for the outputs
2to4Decoder uut(x,y);
initial begin
x = 2'b00;
enable = 1'b0; //keep it off
#10 //wait some time
enable = 1'b1; //turn enable on
#10; //wait some time
x = 2'b01; //input 01
#10; //wait some time
x = 2'b10; //input 10
#10; //then
x = 2'b11; //input 11
#10;
enable = 1'b0; //turn it off
#10;
end
endmodule
You are not instantiating the design properly. Firstly, enable is not connected. enable is not even declared in testbench.
Also, the module name is wrong. Instead of following:
2to4Decoder uut(x,y);
You must have:
decoder2to4 uut(x,enable, y);
Using a reset logic is encouraged to have default values of output. But since this is a combinational circuit, it is not mandatory here.
The inputs can be provided by using a for or repeat loop and increment variable x in it. But this is just for coding efficiency.
Rest of the things seems to be fine. Refer Module instantiation link.
Related
I intended to write and simulate a module performing MAC operation. My code is shown below
module PE # (
parameter DW = 8
)
(
input clk,
input rst_n,
input [DW-1 : 0] cin,
input [DW-1 : 0] w,
output [DW-1 : 0] cin_out,
output [DW-1 : 0] w_out,
output [2*DW : 0] pe_out
);
reg [DW-1 : 0] cin_reg;
reg [DW-1 : 0] w_reg;
reg [2*DW : 0] m_reg;
reg [2*DW : 0] pe_reg;
always #(posedge clk) begin
if(rst_n==1'b0) begin
pe_reg <= 0;
cin_reg <= 0;
w_reg <= 0;
end
else begin
cin_reg <= cin;
w_reg <= w;
m_reg <= cin_reg * w_reg;
pe_reg <= pe_reg + m_reg;
end
end
assign cin_out = cin_reg;
assign w_out = w_reg;
assign pe_out = pe_reg;
endmodule
I used VCS to simulate, however, pe_out kept xxxxxxxx as shown in fig below.
false wave
I have asked my friend to use verilator to simulate, it can work as expected. And if I delete pe_reg <= pe_reg + m_reg, it still works. Therefore, the issue is likely to be caused by the add operation? But I haven't solved it yet.
I'll be appreciate if anyone can give me some instructions. It have confused me for hours.
My tb is written as below.
module tb_PE;
reg clk;
reg rst_n;
reg [7:0] cin;
reg [7:0] w;
wire [7:0] cin_out;
wire [7:0] w_out;
wire [16:0] pe_out;
wire [16:0] pe_out_tmp;
initial begin
clk = 0;
forever begin
#10;
clk = ~clk;
end
end
initial begin
rst_n = 1'b1;
#5;
rst_n = 1'b0;
#10;
rst_n = 1'b1;
#5;
cin = 8'h01;
w = 8'h02;
#15;
cin = 8'h03;
w = 8'h04;
#20;
cin = 8'h05;
w = 8'h03;
#20;
cin = 8'h90;
w = 8'h88;
#20;
cin = 8'h65;
w = 8'h20;
#100;
$finish;
PE PE_U (
.clk(clk),
.rst_n(rst_n),
.cin(cin),
.w(w),
.cin_out(cin_out),
.w_out(w_out),
.pe_out(pe_out)
);
end
As #mkrieger1 mentioned, you have not initialized m_reg. So, the following is happening:
at the first posedge you initialized some of the variables, including pe_reg, while m_reg is still x.
at the second posedge m_reg is still x. Using nonblocking assignment you schedule it to change later, but in this expression pe_reg <= pe_reg + m_reg; it is still x.
as a result, pe_reg becomes x again because m_reg is still x and it will stays same because it is used recursively in the expression.
So, the easiest way to handle it is to initialize m_reg in the same bucket as pe_reg. If for some reason it is not acceptable, you need to delay evaluation of pe_reg for another cycle.
I'm trying to design an elevator controller in SystemVerilog. The code compiles well but the testbench is completely different when I put it in gtkwave.
The controller receives 3 different inputs (one for each of the 3 floors, like buttons of a proper elevator) and passes its output to the elevator engine, which can stay on the same floor, go up or go down by one or two floors.
This is the code for the module:
enum logic [4:0] {fermo, sale, sale2, scende, scende2} motore;
module ascx (input logic x0, x1, x2, clk, reset,
output logic [4:0] y);
enum logic [1:0] {pianoterra, primopiano, secondopiano} piani;
logic [1:0] pianoatt, pianoprox;
always_ff#(posedge clk, posedge reset)
if(reset) pianoatt <= pianoterra;
else pianoatt <= pianoprox;
always_comb begin
if(x1) pianoprox = primopiano;
else if(x0) pianoprox = pianoterra;
else if(x2) pianoprox = secondopiano;
end
always #(*) begin
case(pianoatt)
pianoterra: begin
if(x0) assign y = fermo; /*assign y = 5'b00001;*/
if(x1) assign y = sale; /*assign y = 5'b00010;*/
if(x2) assign y = sale2; /*assign y = 5'b00100;*/
end
primopiano: begin
if(x0) assign y = scende; /*assign y = 5'b01000;*/
if(x1) assign y = fermo; /*assign y = 5'b00001;*/
if(x2) assign y = sale; /*assign y = 5'b00010;*/
end
secondopiano: begin
if(x0) assign y = scende2; /*assign y = 5'b10000;*/
if(x1) assign y = scende; /*assign y = 5'b01000;*/
if(x2) assign y = fermo; /*assign y = 5'b00001;*/
end
default assign y = fermo;
endcase
end
endmodule
Here's the testbench:
module tst_ascx();
logic clk, reset, x0, x1, x2;
logic [4:0] y;
ascx dut(clk, reset, x0, x1, x2, y);
always begin
clk=0; #10;
clk=1; #10;
end
initial begin
$dumpfile("ascx.vcd");
$dumpvars;
reset=1; x0=0; x1=0; x2=0; #10;
reset=0; x0=1; x1=0; x2=0; #10;
x0=0; x1=1; #10;
x1=0; x2=1; #10;
x0=1; x2=0; #10;
x0=0; x2=1; #10;
x1=1; x2=0; #10;
x0=1; x0=0; #10;
end
endmodule
And here the gtkwave display:
The clock, as shown in the image, is not correct.
The input x0 should not be periodic, it simply represents a button being pressed at some time.
I can't say if for the rest the module is working properly, because of these two problems.
You connected signals to your dut incorrectly. The 1st signal in the dut instance (clk) is connected to the 1st port in the module declaration (x0), etc.
To avoid this type of common mistake, use connection-by-name instead of connection-by-position. Refer to IEEE Std 1800-2017, section 23.3.2.2 Connecting module instance ports by name.
Change:
ascx dut(clk, reset, x0, x1, x2, y);
to:
ascx dut (
.clk (clk),
.reset (reset),
.x0 (x0),
.x1 (x1),
.x2 (x2),
.y (y)
);
Unrelated to your problem: you should not use the assign keyword in the always block. Refer to this explanation of a procedural continuous assignment
I made 4_to_1 MUX with 2_to_1 MUX. I used always syntax. The output is delayed one time unit, but I don't know why.
When I change the always condition of 4_to_1 MUX's module sel to *, it works well. Why is this working?
module MUX_2_to_1 (
a0,a1,sel,out);
input [3:0]a0;
input [3:0]a1;
input sel;
output reg [3:0]out;
always #(sel)
begin
if (sel == 0)
out <= a0;
else if (sel == 1)
out <= a1;
end
endmodule
*
module MUX_4_to_1(
x0,x1,x2,x3,sel,out);
input [3:0]x0;
input [3:0]x1;
input [3:0]x2;
input [3:0]x3;
input [1:0]sel;
output reg [3:0]out;
wire [3:0]w0;
wire [3:0]w1;
MUX_2_to_1 m0 (x0,x1,sel[0],w0);
MUX_2_to_1 m1 (x2,x3,sel[0],w1);
always #(sel)
begin
if(sel[1] == 0)
out <= w0;
else if (sel[1] == 1)
out <= w1;
end
endmodule
*
`timescale 100ps/1ps
module Testbench_Mux;
reg [3:0]x0;
reg [3:0]x1;
reg [3:0]x2;
reg [3:0]x3;
reg [1:0]sel;
wire [3:0]out;
MUX_4_to_1 m0 (x0,x1,x2,x3,sel,out);
initial
begin
x0 = 4'b0001; x1 = 4'b0010; x2 = 4'b0100; x3 = 4'b1000;
#0 sel = 2'b00;
#5 sel = 2'b01;
#5 sel = 2'b10;
#5 sel = 2'b11;
#5 $stop;
end
endmodule
You are not using recommended Verilog coding practices for combinational logic. One problem is that you used an incomplete sensitivity list:
always #(sel)
Since there are 2 other signals, w0 and w1, which are read in the always block, they must also be in the sensitivity list. The verbose way to do this is:
always #(sel or w0 or w1)
The preferred way to do this is to use the compact * syntax:
always #(*)
This assures that the always block will be triggered when any change occurs to any signal read in the block.
Another issue is that you should always use blocking assignments for combinational logic. There is ample documentation out there as to the reason.
Change <= to =:
always #(*)
begin
if(sel[1] == 0)
out = w0;
else if (sel[1] == 1)
out = w1;
end
If you don't follow these recommendations, you get undesired simulation results.
You should change your MUX_2_to_1 module as well.
My code is compiling well, but it does not work when i simulate it.
It displays "error loading design".
i think that input and output port is wrong among these modules.
but i can not find them..
please help me where the error is in my code.
module tb_modulo_60_binary;
reg t_clk, reset;
wire [7:0] t_Y;
parameter sec = 30;
always #(sec) t_clk = ~t_clk;
modulo_60_binary M1 (t_Y, t_clk, reset);
initial begin
t_clk = 1; reset =1; #10;
reset = 0; #3050;
$finish;
end
endmodule
module modulo_60_binary(y, clk, reset);
output [7:0] y;
input reset, clk;
wire TA1, TA2, TA3, JA2, JA4;
reg [7:0] y;
assign TA1 = 1;
assign TA2 = (~y[6]) && y[4];
assign TA3 = (y[5] && y[4]) || (y[6] && y[4]);
assign JA2 = ~y[3];
assign JA4 = y[1]&&y[2];
jk_flip_flop JK1 (1, 1, clk, y[0]);
jk_flip_flop JK2 (JA2, 1, y[0], y[1]);
jk_flip_flop JK3 (1, 1, y[1], y[2]);
jk_flip_flop JK4 (JA4, 1, y[1], y[3]);
t_flip_flop T1 (TA1, clk, y[4]);
t_flip_flop T2 (TA2, clk, y[5]);
t_flip_flip T3 (TA3, clk, y[6]);
always #(negedge clk)
begin
if(reset)
y <= 8'b00000000;
else if(y == 8'b01110011)
y <= 8'b00000000;
end
endmodule
module t_flip_flop(t, clk, q);
input t, clk;
output q;
reg q;
initial q=0;
always #(negedge clk)
begin
if(t == 0) q <= q;
else q <= ~q;
end
endmodule
module jk_flip_flop(j, k, clk, Q);
output Q;
input j, k, clk;
reg Q;
always #(negedge clk)
if({j,k} == 2'b00) Q <= Q;
else if({j,k} == 2'b01) Q <= 1'b0;
else if({j,k} == 2'b10) Q <= 1'b1;
else if({j,k} == 2'b11) Q <= ~Q;
endmodule
Your y signal in modulo_60_binary is being driven in two places:
By bit JK# and T# instances
The reset logic that assigns all bits of y to zeros
Flops and comb-logic must have one clear driver. This is one of the fundamental differences between software and hardware languages.
The rest of my answer assuming the use of the JK and T flops are a design requirement. Therefore you need to delete the always block that assigns y to zeros and and make y a wire type.
Fixing the logic to the T flops is easy. Simply add a conditional statement. Example:
wire do_rst = reset || (y == 8'b01110011);
assign TA1 = do_rst ? y[4] : 1;
assign TA2 = do_rst ? y[5] : (~y[6]) && y[4];
assign TA3 = do_rst ? y[6] : (y[5] && y[4]) || (y[6] && y[4]);
The JK flops is harder because the output of one flop is the clock of another. I'll advice that the clock input for each JK flop should be clk, otherwise you are asking for a design headache for reset when it's y bits are non power of two minus one values (eg 1,3,7,15). This means you need to re-evaluate your JA# logic and add KA# logic (hint the do_rst from above will help). I'm not going to do the work for you beyond this.
There is the option of the asynchronous reset approach, but for this design I will advice ageist it. The reset pulse could be too short on silicon with the conditional reset for y == a particular value(s), which can result in an undependable partial reset. You could add synthesis constraints/rules to keep the push wide enough, but that is just patching a brittle design. Better to design it robust at the beginning.
FYI: y[7] does not have a driver and the module declaration of instance T3 has a typo.
This is not about actually creating a verilog module with inout ports. There are tons of posts I've found about that.
What I am stuck on is, if I have a blackbox module with an inout port, let's says it's defined like
module blackbox(inout a, in b, in c)
And I want to instantiate it in a different module like
module myModule(input reg inReg, output wire outWire)
blackbox(outWire);
How do I also drive the blackbox with the inReg and have it output on the outWire at different times? I don't know of a way to connect one and disconnect the other. This is obviously oversimplified. What I really have is below, but it's more complicated.
module sram_control(
input wire HCLK,
input wire [20:0] HADDR,
input wire HWRITE,
input wire [1:0] HTRANS,
input wire [7:0] HWDATA,
output reg [7:0] HRDATA
);
parameter IDLE_PHASE = 2'b00;
parameter WRITE_PHASE = 2'b01;
parameter READ_PHASE = 2'b10;
parameter IDLE = 2'b00;
parameter NONSEQ = 2'b10;
parameter READ = 1'b0;
parameter WRITE = 1'b1;
reg current_state, next_state;
wire CE, WE, OE;
reg [20:0] A;
wire [7:0] DQ;
reg [7:0] DQ_tmp1;
wire [7:0] DQ_tmp2;
async the_mem(.CE_b(CE), .WE_b(WE), .OE_b(OE), .A(A), .DQ(DQ));
always #(posedge HCLK) begin
if(current_state == IDLE_PHASE) begin
next_state <= HTRANS == NONSEQ? (HWRITE == WRITE? WRITE_PHASE : READ_PHASE) : IDLE_PHASE;
A <= HADDR;
end
else if(current_state != IDLE_PHASE) begin
if(HTRANS == NONSEQ) begin
if(HWRITE == WRITE) begin
next_state <= WRITE_PHASE;
end
else begin
next_state <= READ_PHASE;
end
end
else next_state <= IDLE_PHASE;
end
// we never get here
else next_state <= IDLE_PHASE;
end
always#(posedge HCLK) begin
if(current_state == READ_PHASE) HRDATA <= DQ;
end
assign CE = current_state != IDLE_PHASE? 1 : 0;
assign WE = current_state != IDLE && HWRITE == WRITE? 1 : 0;
assign OE = current_state != IDLE_PHASE? 1 : 0;
always#(posedge HCLK) current_state <= next_state;
endmodule
What I need is a way to assign HWDATA to the async module when I want to write to it, and I need a way to assign the output of the async module to HRDATA when I want to read from the async.
For all inout ports, you can read the data at any time. But for driving that net, generally tri state buffers are used. The reason for that is the same net may be shared with multiple modules and since the net is on inout type, to remove conflict of multiple driver, the tri state buffers are used.
For the same above image, here is the code.
assign io = t ? i : 1'bz; // To drive the inout net
assign o = io; // To read from inout net
As you say, this isn't a Verilog question, it's a logic design question.
You need to implement a tri-state driver to drive DQ:
assign DQ = WE ? 8'bz : HWDATA;
(assuming WE is 1'b0 when you are doing a write).
In general I would avoid tri-state logic inside an IC/FPGA, because not only is there the obvious problem when more than one driver drives a bus, it is also a problem if nothing drives the bus (some gates get floating inputs). There are also further problems in IC design. However, presumably you have not choice in this case; presumably you did not design module async. (If you did - take out the inout.)