why output of a module can't reach from outside module - verilog

Question

I write two module by Verilog.
first module is 4 bit counter:
module ASYNCHRONOUS_COUNTER( clk, res, out);
input clk;
input res;
output[3:0] out;
reg[3:0] out;
wire clk;
wire res;
initial
out = 4'b0;
always #(negedge clk or posedge res)
if(res) begin
out[0] <= 1'b0;
end else begin
out[0] <= ~out[0];
end
always #(negedge out[0] or posedge res)
if(res) begin
out[1] <= 1'b0;
end else begin
out[1] <= ~out[1];
end
always #(negedge out[1] or posedge res)
if(res) begin
out[2] <= 1'b0;
end else begin
out[2] <= ~out[2];
end
always #(negedge out[2] or posedge res)
if(res) begin
out[3] <= 1'b0;
end else begin
out[3] <= ~out[3];
end
endmodule
second module use first module :
module tripleInputClk(clk,tripledClk);
input clk;
wire clk;
output tripledClk;
wire tripledClk;
wire res;
wire[3:0] out;
reg temp;
initial
temp <= 1'b0;
//assign out = 3'b0;
assign res = ~out[3] & ~out[2] & out[1] & out[0];
ASYNCHRONOUS_COUNTER myCounter(
.clk(clk),
.res(res),
.out(out)
);
always #(posedge res)
begin
temp <= ~temp;
end
assign tripledClk = temp;
endmodule
first module works correctly, but when I compiled it and made it's wave form ,I understood that outputs of first module doesn't pass correctly and value of 'res' always equal '0'.

Answer 1

Here, res is declared as wire in your tripleInputClk module.
I simulated your code and observed that the signal tripledClk goes HIGH after three clock pulses. Thereby, suspecting that a posedge of res signal must occur. But, res is in continuous assignment statement. As soon as res becomes HIGH, the reg out changes (#(posedge res)) and again makes res LOW; all this in a single time stamp. So you are not able to view transition of res signal.
Also, after that, the tripledClk signal does not toggle as expected, I guess.
One way out is to declare res as reg in tripleInputClk module and remove it from continuous assignment. Instead, make it work on the edge of clock signal only.
This is because, reg is used to store values. Here, there is a circular dependency of res on out and vice-versa (i.e. out is also dependent on res). Henceforth, it creates some sort of confusing conditions(I would not term it as a race around condition exactly).
When you'll proceed to synthesis (even though initial block is not synthesizable here..!), the tool may issue this circular dependency warning. And, proper hardware may not be formed.
I've modified your code and provided a testbench to it. The only change is the one that I described here, i.e. res signal. Kindly go through the link below. The tripledClk is now also working fine as (3*frequency_of_clk).
Link to EDAPlayground.