How to create positive edge detector behavioural code? - verilog

Question

I'm currently trying to code a positive edge detector that changes its output every time a positive edge is detected. I succeeded in building one with gate-level modelling, but now I need to build it using behavioral modelling. I tried building it using this foundation:
module pos_edge_det ( input sig,
input clk,
output pe);
reg sig_dly;
always # (posedge clk) begin
sig_dly <= sig;
end
assign pe = sig & ~sig_dly;
endmodule
I tried making code where in every positive edge it detects on the input, the output will always invert:
module posedgedet(in, out, clk, res);
input wire in,clk,res;
output wire out;
always # (posedge in, posedge clk)
begin
out <= ~out;
end
endmodule
When compiling, it returned this following error
Error: C:/Modeltech_pe_edu_10.4a/examples/pos edge detect.v(8): (vlog-2110) Illegal reference to net "out".
What does this error mean, and how do you properly use the always code to detect a positive edge on both input and clock pulse?

Answer 1

The error means that you can not declare out as a wire when you assign to it inside an always block. You need to declare out as a reg. I posted your module on edaplayground and compiled it on several simulators, one of which produced this slightly more specific error message:
out is declared here as wire.
At least that gives you a hint that there is something wrong with using wire.
There is also a problem with this line:
always # (posedge in, posedge clk)
That will not be synthesized into a flip-flop.
I think you are looking for a module which will detect a posedge on sig and generate an output pe which will be a single-clock wide pulse and also generate an output out which will toggle every time a posedge on sig is seen. I'm assuming your res signal is a reset. I also included a simple testbench.
module pos_edge_det (
input sig,
input clk,
input res,
output pe,
output reg out
);
reg sig_dly;
always # (posedge clk or posedge res) begin
if (res) begin
sig_dly <= 0;
end else begin
sig_dly <= sig;
end
end
assign pe = sig & ~sig_dly;
always # (posedge clk or posedge res) begin
if (res) begin
out <= 0;
end else if (pe) begin
out <= ~out;
end
end
endmodule
module tb;
reg clk, res, sig;
wire pe, out;
initial begin
clk = 0;
forever #5 clk =~clk;
end
pos_edge_det dut (
// Inputs:
.clk (clk),
.res (res),
.sig (sig),
// Outputs:
.out (out),
.pe (pe)
);
initial begin
sig = 0;
res = 1;
#20 res = 0;
repeat (10) #30 sig = ~sig;
#5 $finish;
end
endmodule