Design a counter with a count sequence based on your ID number as follows: write down your student ID, append two 0’s and then append your ID with each digit incremented modulo 10. For example if your student ID is 27273289, then the count sequence is 272732890038384390 and then back to the start. Implement your design with at most 5 flip-flops using Verilog on a DE2 board. Show the result on a 7 segment display using HEX. How do I go about this?
5 flip-flops implies 32 states. Your sequence 272732890038384390 is 19 long.
Build a state machine which counts from 0 to 18, looping back to 0 on completion.
Then use a look up table (combinatorial logic) to decode state into an output value.
Update question with code if you get stuck, then we can help with the programming problem.
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I need to construct a DFA which recognises all the strings made solely from 0s and 1s, so that thay have an even number of zeros and number of ones divisible by 3. I found an automaton for the case of even number of 0s and even number of 1s:
I tried going from here by adding some states, changing branches, etc.. However I remained unsuccessful usually losing track of what's the automaton doing beacuse of branches and states I'd add. Any help would be greatly appreciated.
You need states which record the divisibility by 2 and by 3, which means you need 6 states. Just call them 0|0, 1|0, 0|1, 1|1, 0|2, 1|2. The first digit tells you that when you reach the state, you have an even or odd number of zeros, the 2nd digit tells you that when you reach the state, you have a number of 1s that, when divided by 3, give the given modulus.
Your state diagram contains:
0|x --0--> 1|x
1|x --0--> 0|x
y|0 --1--> y|1
y|1 --1--> y|2
y|2 --1--> y|0
The start state is 0|0, which is also the only stop state.
The important bit to understand is that each state records the the modulus of the number of zeros or ones read when divided by 2, respectively 3. The 0|0 is then modulus 0 in both cases, which is the accepting criteria. This all works, because the number of different states to keep track of is finite. The name DFA tells us already that it would not work for an infinite number of states to track.
One way to view it is that the problem asks for the intersection of 2 languages: one containing an even number of zeroes and another having the number of ones divisible by 3. A way to approach this is to make DFAs for both the languages and then make another DFA which keeps track of the pair of states in each DFA when an input symbol is read.
I have used 'e' and 'o' to denote that the number of zeroes is even or odd respectively. The second digit in each of the states defines the remainder obtained by dividing the number of ones by 3.
I've taken a project using verilog. We have two 4-bits number, a multiplexer(S0,S1) and four module(adder,substractor,and,xor). Output is 4 bit. I think it seems simple alu. I have written a verilog code that contains all of them as modules. I have assigned pins to DE0 board. As you can see, the output can be seen on leds. There is no problem about that. But, how the output can be displayed on Seven Segment Display instead of LEDs? However, the result should be hexadecimal instead of binary. I have also pins about seven segment display, so I think I will implement them like the leds. I'm new about verilog. It will be my first program.
If S is 0 (00), adder result will be seen on LEDs.
If S is 1 (01), subtraction result will be seen on LEDs.
If S is 2 (10), AND operation result will be seen on LEDs.
If S is 3 (11), XOR operation result will be seen on LEDs.
A seven segment display is really just 7 LEDs in a figure 8 pattern (with a 8th LED for the decimal point). As such, you need only drive the pin attached to that segment of the display LOW to light up the segment (See the handbook on the DE0, Section 4.3, for the pins attached to the seven segment display: ftp://ftp.altera.com/up/pub/Altera_Material/Boards/DE0/DE0_User_Manual.pdf ). Now, this means you have control over each segment but just driving your 4 bit number into the display wont product something you can easily read. For this, youre going to need a converter from your 4bit value into a 7bit values representing the pattern to light the seven segment up (Ie, if your output is 4'b0001, you want your seven segment to display a 1, so you need to convert the 4'b0001 into a 7bit value that will result in a 1 being displayed). I think this is a worthy design challenge for you to take on as you learn Verilog, so I will not provide code for a 4-bit to seven segment display module. But if you run into any issues creating your own; feel free to comment to this answer and we can try and help. Or make a new question if its a big issue.
I would create a finite state automaton that recognizes the language of strings of 0 and 1 that don't contain 3 consecutive zeros.
I tried to do the following automaton but isn't complete as, for example, it doesn't recognize the string: 1001110
How can I change it? For the rest, my reasoning to solve the exercise is that correct?
Thanks so much
i made this in paint so not looking nice but,try below automation.
Your starting state, q0, is a state that is not reached by reading a zero. As you correctly modeled in your automaton, from the state q0 you must allow the automaton to read up to two zeros, hence you need states q1 (reached by reading exactly one consecutive zero) and q2 (reached by reading exactly two consecutive zeros).
Whenever you read a 1 you will be in a state that was not reached by reading a zero.
Now a question is, how many states do you need?
It is permissible to have more than one end state in a finite automaton. In this case you must have more than one end state, because any time you read a 1 you must reach a state that permits two subsequent consecutive zeros to be read, whereas every time you read a zero you much reach a state that does not permit two subsequent consecutive zeros to be read, and your language has strings that end in zero as well as strings that end in 1.
I'm working on a project where I sample a signal with an ADC, that represents values as 14 bit words. I need to scale the values to 8 bit words. What's a good way to go about this in general. By the way, I'm using an FPGA so I'd like to do it in "hardware" rather than a software solution. Also in case you're wondering the chain of events will be: sample analog signal, represent sample value with 14 bit word, scale 14 bit word to 8 bit word, transmit 8 bit word with UART to PC COM1.
I've never done this before. I was assuming you use quantization levels, but I'm not sure what an efficient circuit for this operation would be. Any help would be appreciated.
Thanks
You just need an add and a shift:
val_8 = (val_14 + 32) >> 6;
(The + 32 is necessary to get correct rounding - you can omit it but you will get more truncation noise in your signal if you do.)
I think you just drop the six lowest resolution bits and call it good, right? But I might not fully understand the problem statement.
Paul's algorithm is correct, but you'll need some bounds checking.
assign val_8 = (&val_14[13:5]) ? //Make sure your sum won't overflow
8'hFF : //Assign all 1's if it will
val_14[13:6] + val_14[5];
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Why does the indexing start with zero in 'C'?
Why do prevailing programming languages like C use array starting from 0? I know some programming languages like PASCAL have arrays starting from 1. Are there any good reasons for doing so? Or is it merely a historical reason?
Because you access array elements by offset relative to the beginning of the array.
First element is at offset 0.
Later more complex array data structures appeared (such as SAFEARRAY) that allowed arbitrary lower bound.
In C, the name of an array is essentially a pointer, a reference to a memory location, and so the expression array[n] refers to a memory location n-elements away from the starting element. This means that the index is used as an offset. The first element of the array is exactly contained in the memory location that array refers (0 elements away), so it should be denoted as array[0]. Most programming languages have been designed this way, so indexing from 0 is pretty much inherent to the language.
However, Dijkstra explains why we should index from 0. This is a problem on how to denote a subsequence of natural numbers, say for example 1,2,3,...,10. We have four solutions available:
a. 0 < i < 11
b. 1<= i < 11
c. 0 < i <= 10
d. 1 <= i <= 10
Dijkstra argues that the proper notation should be able to denote naturally the two following cases:
The subsequence includes the smallest natural number, 0
The subsequence is empty
Requirement 1. leaves out a. and c. since they would have the form -1 < i which uses a number not lying in the natural number set (Dijkstra says this is ugly). So we are left with b. and d. Now requirement 2. leaves out d. since for a set including 0 that is shrunk to the empty one, d. takes the form 0 <= i <= -1, which is a little messed up! Subtracting the ranges in b. we also get the sequence length, which is another plus. Hence we are left with b. which is by far the most widely used notation in programming now.
Now you know. So, remember and take pride in the fact that each time you write something like
for( i=0; i<N; i++ ) {
sum += a[i];
}
you are not just following the rules of language notation. You are also promoting mathematical beauty!
here
In assembly and C, arrays was implemented as memory pointers. There the first element was stored at offset 0 from the pointer.
In C arrays are tied to pointers. Array index is a number that you add to the pointer to the array's initial element. This is tied to one of the addressing modes of PDP-11, where you could specify a base address, and place an offset to it in a register to simulate an array. By the way, this is the same place from which ++ and -- came from: PDP-11 provided so-called auto-increment and auto-decrement addressing modes.
P.S. I think Pascal used 1 by default; generally, you were allowed to specify the range of your array explicitly, so you could start it at -10 and end at +20 if you wanted.
Suppose you can store only two bits. That gives you four combinations:
00 10 01 11 Now, assign integers to those 4 values. Two reasonable mappings are:
00->0
01->1
10->2
11->3
and
11->-2
10->-1
00->0
01->1
(Another idea is to use signed magnitude and use the mapping:
11->-1 10->-0 00->+0 01->+1)
It simply does not make sense to use 00 to represent 1 and use 11 to represent 4. Counting from 0 is natural. Counting from 1 is not.