i want to shift a signal by fixed number of clock cycles. I receive the signal from adc. kindly let me know how to implement this
HINT: Not a full answer
A 8 bit flip-flop in verilog might look like:
reg [7:0] a;
always #(posedge clk, negedge rst_n) begin
if (~rst_n) begin
// Active Low Reset condition
a <= 'b0;
end
else begin
a <= input_eight_bit;
end
end
To delay for multiple clock cycles you need multiple flip-flops feeding from one to the next. This creates a pipe line or delay line.
Related
I'm trying to create a state machine for the GCD algorithm(subtraction method), and I need to put the values(wires) of my numbers to a register to work with the algorithm, but I don't want for each value change to assimilate into the registers.
in other words:
module GCD_R (u,v,out,nrst,act,clk);
input [31:0] A,B;
input clk,act,rst;
output reg [31:0] out;
reg[4:0] state,next_state;
reg[31:0] A_reg,B_reg,Aint_reg,Bint_reg;
parameter IDLE = 4'b0001;
parameter ABIG = 4'b0010;
parameter BBIG = 4'b0100;
always #(A,B)
begin
A_reg<=A
B_reg<=B
end
always #*
case (state)
IDLE: begin
but this definition is problematic since if someone changes the values of A or B, it will move them to the registers every time and I don't want that, basically I need some condition that will move the values to the registers only on initialization, how do I do that?
Usually for such issues clocks are used. You even have it in parameters. So, use it:
always #(posedge clk) begin
A_reg<=A
B_reg<=B
end
Usually for such designs, Clock Edges along with the reset signal is used.
always # (posedge clk, negedge rst)
begin
if (!rst)
begin
// For initialisation
A_reg<=A
B_reg<=B
end
else
begin
// For non initialisation operation to retail value
A_reg<=A_reg;
B_reg<=B_reg;
end
end
I'm trying to write a roll shift/ ring counter that takes two switches as the clocks in verilog.
My code is as follows:
module roll(CLK1, CLK2, LEDS);
input CLK1;
input CLK2;
output [3:0] LEDS;
reg [3:0] LEDS;
initial
begin
LEDS = 4'b0001;
end
always#(posedge CLK1 or posedge CLK2)
begin
if(CLK1)
begin
LEDS[3]<=LEDS[2];
LEDS[2]<=LEDS[1];
LEDS[1]<=LEDS[0];
LEDS[0]<=LEDS[3];
end
// Roll Right
if(CLK2)
begin
LEDS[3]<=LEDS[0];
LEDS[2]<=LEDS[3];
LEDS[1]<=LEDS[2];
LEDS[0]<=LEDS[1];
end
end
endmodule
I tried using two always blocks, but then figured out that I cannot do that. and when I have the posedge CLK2 in the always statement, the leds on my FPGA all stay on.
Remember Verilog is not a programming language it is a hardware description language.
And when coding for synthesis, you will only be successful if you write code that can be instantiated with actual gates. So writing an always block with sensitivity to edges of two different signals can't be synthesized unless the response to one of the two signals has the effect of a RESET or PRESET operation.
Your code also logically doesn't do what it seems you want to. Consider what your code says will happen if there is a rising edge on CLK2 when CLK1 is already high (or vice versa). Your lights will roll left and then immediately roll right gain, resulting in no change.
A more usual approach would be to have a clock running much faster than the UP and DOWN inputs are expected to change, and use that to drive the logic. For example
module roller(input clk, input rst, input UP, input DOWN, output reg LEDS[3:0]);
reg UP1, DOWN1;
always #(posedge clk or posedge rst)
if (rst) begin
LEDS[3:0] <= 4'b0001;
end
else
begin
UP1 <= UP;
DOWN1 <= DOWN;
if (UP & ~UP1) begin
LEDS[3:0] <= {LEDS[2:0], LEDS[3]};
end
else if (DOWN & ~DOWN1) begin
LEDS[3:0] <= {LEDS[0], LEDS[3:1]};
end
end
endmodule;
Notice that this gives priority to UP. If both UP and DOWN are asserted, the pattern will roll "up" rather than down. If you want a different behavior, you'd have to modify the code to achieve it.
Removing #2 reset after monitor statement makes the code not to work.The output just stands at 0 x. Whereas including it works fine. Why?
module counter(out,clock,reset);
input clock,reset;
wire clock,reset;
output [3:0]out;
reg [3:0]out;
always #(posedge clock or negedge clock)
begin
if(reset)
out<=1'b0;
else
out<=out+1;
end
endmodule
module tb();
reg clock,reset;
output [3:0]out;
counter c(out,clock,reset);
initial
begin
clock=0;
reset=1;
end
initial
begin
$monitor("%d %d",$time,out);
#2 reset=0;
end
always
#1 clock=~clock;
initial
#100 $finish;
endmodule
By removing the #2 you create a race condition on reset:
initial reset = 1;
initial reset = 0;
Simulators will often have the the final value of reset the last assignment read in the compiling order. Try merging you initial blocks:
initial
begin
$monitor("%d %d",$time,out);
clock=0;
reset=1;
#2 // <-- optional (and still recommened) if you make the below change
// #(clk) //<-- if you truely want a dual edge triggered flip-flop with synchronous reset
reset=0;
end
Dual edge triggered flip-flop are very uncommon and many synthesizers and FPGAs do not support them. I'm guessing you are intending to have an negative edge triggered flip-flop with an active high asynchronous reset. In this case replace:
always #(posedge clock or negedge clock)
with:
always #(negedge clock or posedge reset)
Hello Friends I still not know how to Generate Delay in Verilog For synthesis and call it any line in Verilog for synthesis...for finding this I write a code but it not works please help me if you know how to Generate Delay and call in any line like a C's Function*......Actually Friends if you tell me why I use for Loop here then my answer is - I want to move pointer inside for loop until and unless they completes its calculation that I made for Delay Generation..
module state_delay;
reg Clk=1'b0;
reg [3:0]stmp=4'b0000;
integer i,a;
always
begin
#50 Clk=~Clk;
end
always #(posedge Clk)
begin
a=1'b1;
delay();
a=1'b0;
delay();
a=1'b1;
end
task delay();
begin
for(i=0;i==(stmp==4'b1111);i=i+1)
begin
#(posedge Clk)
begin
stmp=stmp+1;
end
end
if(stmp==4'b1111)
begin
stmp=4'b0000;
end
end
endtask
endmodule
Actually friends I want this a=1'b0; delay(); a=1'b1; please help I already tried delay Generation Using Counter previously but it not works for me.....If you know same using Counter then please tell me......Thanks
// will generate a delay of pow(2,WIDTH) clock cycles
// between each change in the value of "a"
`define WIDTH 20
reg [`WIDTH:0] counter;
wire a = counter[`WIDTH];
always #(posedge Clk)
counter <= counter + 1;
You have to choose a suitable value for WIDTH according to how much delay you want between changes in a and the rate of your Clk signal
This question is a more succinct version of How to generate delay in verilog using Counter for Synthesis and call inside Always block?.
There is one section of code that I find troublesome:
always #(posedge Clk) begin
a = 1'b1;
delay() ;
a = 1'b0;
end
NB: A good rule to stick to is to always use <= in edge triggered processes.
for now lets think of the delay(); task as #10ns; What we get with the current code would be:
time 0ns a = x;
time 1ns a = 1; //Posedge of clk
time 6ns a = 1; //Waiting on delay
time 11ns a = 0; //Delay completed
Using <= and I think you should see a similar behaviour. However when it comes to synthesis delays like #1ns can not be created and the whole thing will collapse back down to :
always #(posedge Clk) begin
a <= 1'b0;
end
With a hardware description language a good approach is to consider what hardware we want to imply and describe it in the language. The construct always #(posedge Clk) is used to imply flip-flops, that is the output changes once per clock cycle. In the question we have a changing value 3 times, from 1 clock edge I do not know what hardware you are trying to imply.
You can not provide an inline synthesizable delay. For always #(posedge clk) blocks to be synthesizable they should be able to execute in zero time. You need to introduce a state machine to keep state between clock edges. I think I have already provided a good example on how to do this in my previous answer. If the delay is to be programmable then see mcleod_ideafix's answer.
I am very new to HDL language. I have a question about how to program a shift register. (i know i shift to the other direction). Why does the book use wire[N-1:0] r_next? what's drawback of my implementation?
thanks
my first try is as following
module lesson04#(parameter N=8)(
input wire clk, reset,
input wire data,
output wire out
);
reg [N-1: 0] r_reg;
always #(posedge clk or negedge reset)
begin
if(!reset)
r_reg =0;
else
r_reg[0]=data;
r_reg = r_reg<<1;
end
assign out =r_reg[N-1];
endmodule
but the book gives:
module lesson04#(parameter N=8)(
input wire clk, reset,
input wire data,
output wire out
);
reg [N-1: 0] r_reg;
wire[N-1:0] r_next;
always #(posedge clk or negedge reset)
begin
if(!reset)
r_reg =0;
else
r_reg <= r_next;
end
assign r_next= {data, r_reg[N-1:1]};
assign out =r_reg[N-1];
endmodule
First of all, don't forget your begin-ends around sections of code:
else begin
r_reg[0]=data;
r_reg = r_reg<<1;
end
Without this, only r_reg[0]=data will be in the else clause of the if statement. This will work, but is considered bad style due to the blocking statements in a sequential logic description...
Second, for modeling sequential blocks, use nonblocking assignments (<=) or your calculations may 'fall through' (google nonblocking vs blocking for more info). Your example may very well work (did you try it in a simulator?) but if things get more complicated and more variables are added things can break.
always #(posedge clk or negedge reset)
begin
if(!reset)
r_reg <= 0;
else begin // This is horrible! Don't write code like this!
r_reg[0] = data; // blocking
r_reg <= r_reg<<1; // non-blocking
end
end
For the above reason, it is sometimes recommended that combo logic is separated from sequential logic so that you can write nonblocking assignments to registers in sequential blocks, and blocking in combo blocks and never have to worry about the scheduling.
To code in this way, you need to calculate what the next output should be using the current state, hence the r_next bus in the answer. I think it tends to help the synthesis tool out too if all the flip-flops are separated from surrounding combo logic in this way.
Also, if your reset is active low (ie LOW resets ) it should be named as such, eg resetb or reset_n.
Your implementation produces quite a different output from the book's. You should prove this to yourself by constructing a simple testbench to drive your inputs and run a simulation. You will see that the book's output shifts the input data by a single clock cycle, whereas your output shifts the input data by eight clock cycles.
By the way you have indented your always block, I am led to believe that it is not what you wanted. This is how your block really behaves:
always #(posedge clk or negedge reset)
begin
if(!reset) begin
r_reg =0;
end else begin
r_reg[0]=data;
end
r_reg = r_reg<<1;
end
I always explicitly use the begin/end keywords in if/else statements to avoid this confusion.
The way it simulates, r_reg is always 0 because you clobber the 1st assignment (r_reg[0]=data;) with the 2nd (r_reg = r_reg<<1;). Another difference is that the book assigns data to the MSB of the shift register, but you assign it to the LSB.
If you are using decent linting and synthesis tools, you would probably get a bunch of warnings for your code. This would alert you to make some changes.