Removing #2 reset after monitor statement makes the code not to work.The output just stands at 0 x. Whereas including it works fine. Why?
module counter(out,clock,reset);
input clock,reset;
wire clock,reset;
output [3:0]out;
reg [3:0]out;
always #(posedge clock or negedge clock)
begin
if(reset)
out<=1'b0;
else
out<=out+1;
end
endmodule
module tb();
reg clock,reset;
output [3:0]out;
counter c(out,clock,reset);
initial
begin
clock=0;
reset=1;
end
initial
begin
$monitor("%d %d",$time,out);
#2 reset=0;
end
always
#1 clock=~clock;
initial
#100 $finish;
endmodule
By removing the #2 you create a race condition on reset:
initial reset = 1;
initial reset = 0;
Simulators will often have the the final value of reset the last assignment read in the compiling order. Try merging you initial blocks:
initial
begin
$monitor("%d %d",$time,out);
clock=0;
reset=1;
#2 // <-- optional (and still recommened) if you make the below change
// #(clk) //<-- if you truely want a dual edge triggered flip-flop with synchronous reset
reset=0;
end
Dual edge triggered flip-flop are very uncommon and many synthesizers and FPGAs do not support them. I'm guessing you are intending to have an negative edge triggered flip-flop with an active high asynchronous reset. In this case replace:
always #(posedge clock or negedge clock)
with:
always #(negedge clock or posedge reset)
Related
I am trying to generate a pulse from a signal ext_sample_clk. My design currently has 2 clock signals, clk and ext_sample_clk, which I am generating through a testbench. The following is my simplified code. Besides this, I also have the clk and reset generation logic, which I have not shown for simplicity. I can share those if needed.
module tb;
reg clk;
reg rst;
reg ext_sample_clk;
reg ext_sample_clk_r1;
wire ext_sample_pulse_orig;
//clock gen logic
always
begin
clk = 1'b1;
#5; // 10 ns
clk = 1'b0;
#5;
end
// reset gen logic
initial
begin
rst = 1;
#(100);
rst = 0;
end
// ext_sample_clk logic
always
begin
ext_sample_clk = 1'b1;
#50;
ext_sample_clk = 1'b0;
#50;
end
// register the ext_sample_clk logic, should infer a flip flop
always #(posedge clk) begin
if (rst)
ext_sample_clk_r1 <= 0;
else
ext_sample_clk_r1 <= ext_sample_clk; // lhs doesn't appear to be delayed by 1 clock cycle wrt to rhs
end
assign ext_sample_pulse_orig = ext_sample_clk && !ext_sample_clk_r1;
endmodule
I am expecting to see ext_sample_clk_r1 delayed by one clock pulse compared to ext_sample_clk. But the following is what I observe when I run a simulation on Vivado.
Can anyone explain why I am not seeing a clock cycle delay in ext_sample_clk_r1 with reference to ext_sample_clk. Am I missing something ?
Since you want ext_sample_clk_r1 and ext_sample_clk to be synchronous to the same clock (clk), you need to drive them both off of posedge clk, using nonblocking assignments (<=):
initial begin
ext_sample_clk = 1'b1;
forever begin
repeat (10) #(posedge clk);
ext_sample_clk <= ~ext_sample_clk;
end
end
Here is a running example on edaplayground.
The most probably way of getting the results you see is by using a blocking assignment to ext_sample_clk instead of a non-blocking assignment. Your testbench needs to follow the same rules as if it were part of the design to avoid race conditions. Use a non-blocking assignment or have your testbench apply signals on the opposite edge.
All my testbench is trying to do is verify whether or not the LED signal went high, but on Modelsim when I try and simulate it, the clock doesn't even start, but it initializes to zero. I can also step through my design so I don't appear to have an infinite loop or anything like that. Is there anything obviously wrong here, especially with regards to clock initialization and generation?
`timescale 1ns/100ps
module fir_filter_tb();
reg clk, reset_n;
reg led;
top top_level (
.clk(clk),
.reset_n(reset_n),
.led(led)
);
initial
begin
$display($time, " << Starting the Simulation >>");
clk = 1'b0; // at time 0
reset_n = 0; // reset is active
led = 0; // output is low
#10 reset_n = 1'b1; // at time 20 release reset
end
always #10 clk = ~clk;
always
begin
if (led == 1'b1) begin
$write($time, "Filter Successful");
end else begin
$write($time, "bleh you suck");
end
end
endmodule : fir_filter_tb
The problem is with the always block with led in it. Since there is no timing control, it prevents time from advancing (time remains stuck at 0). It creates an infinite zero-time loop.
One way to fix it is to use:
always #*
This will only trigger the block when led changes.
Do RHS signals in an assignment ,inside always block will be added to senstivity list ? if that is true, may i know, why the following code is not working ?
`timescale 1ns/1ps
module tb();
reg clk=0;
initial begin
#10 clk = 1;
#1000;
$finish();
end
always#(*)begin
#10 clk=!clk;
end
initial begin
$recordfile("wave.trn");
$recordvars();
end
endmodule
Your code does not working for a different reason:
An always block is not sensitive to signal changes until all actions have finished.
Thus after your clock has toggled, the always block waits for a new clock event, which is not forthcoming.
To generate a clock you should use something like:
initial
begin
clk = 1'b0;
forever
#(CLK_PERIOD/2) clk = ~clk;
end
i want to shift a signal by fixed number of clock cycles. I receive the signal from adc. kindly let me know how to implement this
HINT: Not a full answer
A 8 bit flip-flop in verilog might look like:
reg [7:0] a;
always #(posedge clk, negedge rst_n) begin
if (~rst_n) begin
// Active Low Reset condition
a <= 'b0;
end
else begin
a <= input_eight_bit;
end
end
To delay for multiple clock cycles you need multiple flip-flops feeding from one to the next. This creates a pipe line or delay line.
The following code is written for an asynchronous counter. The program compiles fine but the counter value doesn't increment after 1. What am I doing wrong?
Here is the code:
//TOP
module CounterWithDivider(clk,reset,temp,q);
input clk,reset;
output [3:0]q;
output reg [3:0]temp;
reg [3:0]clkDivider;
TFF a(clkDivider,clk,reset,q[0]);
TFF b(clkDivider,q[0],reset,q[1]);
TFF c(clkDivider,q[1],reset,q[2]);
TFF d(clkDivider,q[2],reset,q[3]);
always #(posedge clk or negedge reset)
begin
if(~reset || clkDivider==12)
clkDivider<=0;
else
if(clk)
begin
clkDivider<=clkDivider+1;
temp<=clkDivider;
end
end
endmodule
// T flip flop
module TFF(clkDivider,clk,reset,q);
input clk,reset;
input [3:0]clkDivider;
output reg q;
always #(posedge clk or negedge reset)
begin
if(~reset)
q<=0;
else
if(clkDivider==11)
q<=1;
end
endmodule
A T-FlipFlop, or toggle flop should toggle its output when enabled, you just have:
if(clkDivider==11)
q<=1;
Replace q<=1 with q<=~q to make it toggle when enabled.
As you mentioned, this is an asynchrous counter. The reason your Verilog simulation is not doing what you want is that TFF instance b is trying to sample its data input (clkDivider) using a different clock signal. clkDivider is clocked by signal clk, but you are trying to sample it using a different clock signal (q[0]).
You need to either find a way to synchronize the clkDivider signal into each of the other 3 clock domains, or use a fully synchronous design.