Verilog : Can't understand the resulting simulation (delay, blocking/non blocking) - delay

Question

I'm studying the Verilog language (I have already worked with VHDL) and I don't understand the simulation of this following code :
module exam2011;
integer a,b,c,d;
always
begin
c = #1 a;
#2 b=a;
d = a;
end
initial
begin
a = 0; b = 0; c = 0; d = 0;
#1 a=1;
#2 a=2;
#2 a=3;
#2 a=4;
#2 a=5;
end
initial $monitor($time, “a=%d, b=%d, c=%d, d=%d”,a,b,c,d);
endmodule
The result :
# 0a= 0, b= 0, c= 0, d= 0
# 1a= 1, b= 0, c= x, d= 0
# 3a= 2, b= 1, c= x, d= 1
# 4a= 2, b= 1, c= 1, d= 1
# 5a= 3, b= 1, c= 1, d= 1
# 6a= 3, b= 3, c= 1, d= 3
# 7a= 4, b= 3, c= 3, d= 3
# 9a= 5, b= 5, c= 3, d= 5
# 10a= 5, b= 5, c= 5, d= 5
First, I don't know if I think in the good way : when we change the value of "a" AND the value of "b" and "d" (which are "a") at the same time, how are theses changes performed ?
Also, I don't really understand how to interpret the delay command # after the assignment "=".
Thanks for your help.

Answer 1

Output always depends upon the simulator. 'always' and 'initial' statements are executed in parallel. Even though it looks parallel to us, its is executed in sequence by simulator in the same time stamp.
After all the events in the current time stamp are done, simulator will increment the time stamp. In your code, it looks like 'always' statement is executed before 'initial' statement. Let me try to explain bit clearly.
c = #1 a;
this statement is equivalent to
temp = a; //sample the value of 'a'
#1; // Wait for 1 unit of time
c = temp; //assign the sampled value to 'c'
since 'always' statement enters 1st to simulator queue, it samples value of 'a' which is 'x' and stores it in temporary variable at 0th time. Then it enters 'initial' statement and assigns 0 to 'a','b','c' and 'd'. After #1 time unit, sampled value of 'a' which is 'x' is assigned to 'c' in 'always' statement.
#2 b = a;
this statement is equivalent to
#2 //Wait for 2 time unit
b = a //sample the value of 'a' and assign to b
After 3 time unit, since 'always' block is in top of the simulator queue, value of 'a' will still be '1' and it gets assigned to 'c'. After this 'initial' statement is executed and value of '2' is assigned to 'a'. Rest of the output, behaves in the same fashion. Hope this helps.

Answer 2

As I said earlier, Output depends on the simulator. I think for the time stamp #9, 'initial' block went 1st to the simulator queue. So it updated the 'a' to 5. In the same time stamp 'always' block is executed after 'initial' block. So 'c' and 'd' are assigned with updated value of 'a' which is '5'.
Since the time stamp is still #9, this value of 'a' which is '5' is sampled and gets stored in temporary variable. This is later assigned to 'c' at time stamp #10. Hope this make sense.
So this is not a good way of coding. This results in ambiguous results. In order to illustrate this ambiguous result, I can given an example. Consider following codes.
always#(posedge clk)
begin
cnt = cnt+1;
end
always#(posedge clk)
begin
A = cnt;
end
If the initial value of 'cnt' is 40, what is the value of 'A' in next clock cycle. See, now the output depends on the simulator. It depends on which 'always' block goes 1st to the simulator queue. If the 1st 'always' block is executed 1st, 'A' value is '41' else it is '40'. This can be removed by using non-blocking statements "<=".
always#(posedge clk)
begin
cnt <= cnt+1;
end
always#(posedge clk)
begin
A <= cnt;
end
Now 'A' will be 40 irrespective of simulator. Hope this helps.