can not have such operands in this context
Can someone tell me what is wrong and how to fix it please?
I tried to search the problem on the internet, why can't I add to STD_LOGIC_VECTOR and I didn't find anything that explains right my problem. So here I am asking you guys what's the problem?
entity Modes is
Port ( RST : in STD_LOGIC;
CLK_33MHZ : in STD_LOGIC;
BTN : in STD_LOGIC;
LED : out STD_LOGIC);
end Modes;
architecture Behavioral of Modes is
signal ledstatus : STD_LOGIC;
signal mode : STD_LOGIC_VECTOR(1 downto 0);
signal modestatus : STD_LOGIC_VECTOR (1 downto 0);
begin
process(CLK_33MHZ,RST)
variable cnt : integer range 0 to 33000000;
begin
if(RST = '1') then
cnt := 0;
mode <= "00";
LED <= '0';
ledstatus <= '0';
elsif(rising_edge(CLK_33MHZ)) then
if(BTN = '1') then
elsif(mode = "11") then
mode <= "00";
else
**mode <= mode + "01";** -- the problem in the code
end if;
if(mode = "00") then
LED <= '0';
elsif(mode = "01") then
LED <= '1';
elsif(mode = "10") then
if(cnt = 33000000) then
LED <= not ledstatus;
else
cnt := cnt + 1;
end if;
elsif(mode = "11") then
if(cnt = 330000) then
LED <= not ledstatus;
else
cnt := cnt + 1;
end if;
end if;
end if;
LED <= ledstatus;
end process;
end Behavioral;
A std_logic_vector is just a vector of bits - it isn't necessarily a number. The + operator has no meaning in this context.
You need to explicitly state that it is a number, in your case an unsigned number, and then convert it back to a std_logic_vector:
mode <= std_logic_vector(unsigned(mode) + 1);
When mode is equal to 3, adding 1 will make it wrap back round to 0.
There are plenty of other issues with your code but this will fix that immediate synthesis error.
Related
If the reset signal is '0' then "EN" goes high and "clr" goes low. However, if the reset signal goes high on the rising edge of the clock then "EN" goes low and "clr" goes high. I accomplished this in my code, but i need to delay the output signal produced when reset goes high[ EN = 0/ CLR = 1] for 3 more clock cycles. I tried using a counter, but it produced the same answer.
BEGIN
process ( Reset, Clk)
begin
if Reset = '0' then
En <= '1';
clr <= '0';
elsif rising_edge(Clk) then
if Reset = '1' then
En <= '0';
clr <= '1';
end if;
end if;
end process;
END description;
Delaying signals is done by a 3 bit shift register or in your case 3 chained D-FF.
Shift register as a oneliner:
architecture rtl of myEntity is
signal clr_sr : std_logic_vector(2 downto 0) := "000";
signal en_sr : std_logic_vector(2 downto 0) := "000";
signal clr_delayed : std_logic;
signal en_delayed : std_logic;
[...]
begin
[...]
process(Reset, Clk)
begin
if Reset = '0' then
en <= '1';
clr <= '0';
elsif rising_edge(Clk) then
en <= '0';
clr <= '1';
end if;
end process;
clr_sr <= clr_sr(clr_sr'high - 1 downto 0) & clr when rising_edge(Clock);
en_sr <= en_sr(en_sr'high - 1 downto 0) & en when rising_edge(Clock);
clr_delayed <= clr_sr(clr_sr'high);
en_delayed <= en_sr(en_sr'high);
[...]
end;
Or even shorter with a function sr_left to encapsulate the shift functionality:
clr_sr <= sr_left(clr_sr, clr) when rising_edge(Clock);
I am trying to run a dc motor using spartan 3 fpga board and i need to take out 2 pins from the board as the input pins to my motor driver. I am not able to enable them. i have already declared them as out std_logic and i have also generated a constraint file for them, but after checking the output on those pins i am getting 0volts.
what should I write in the code, do i have to declare them as signals?
please tell me how to enable them in vhdl code. below i have given my vhdl code
`entity dc_motor is
port ( clk : in std_logic;
rst : in std_logic;
io_pin1: out std_logic;
io_pin2 : out std_logic);
end dc_motor;
architecture Behavioral of dc_motor is
begin
process(rst,clk)
variable i : integer := 0;
begin
if rst = '1' then
if clk'event and clk = '1' then
--enable <= '1';
if i <= 1005000 then
i := i + 1;
io_pin1 <= '0';
io_pin2 <= '0';
elsif i > 1005000 and i < 1550000 then
i := i + 1;
io_pin1 <= '1';
io_pin2 <= '0';
elsif i = 1550000 then
i := 0;
end if;
end if;
end if;
end process;
end Behavioral;
`
I have a problem that is caused by this keyboard interface. I'm trying to make a digital piano with a keyboard and an amplifier but the sound does not come as we press the button; there is a ~1 second delay. Can you help me with this problem please? Also when we change the code part
Shift2_next <= Shift1(0) & Shift2(10 downto 1);
to
Shift2_next <= PS2Df & Shift2(10 downto 1);
the key gives the sound instantly as wanted but now the sound does not stop; the break code is corrupted in that case I think. Hope you can help. Thanks.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity keyboard_ctrl is
port(
clk25 : in STD_LOGIC;
PS2C : in STD_LOGIC;
PS2D : in STD_LOGIC;
xkey : out STD_LOGIC_VECTOR(16 downto 1)
);
end keyboard_ctrl;
architecture keyboard of keyboard_ctrl is
signal PS2Cf, PS2Df: std_logic;
signal PS2Cf_next, PS2Df_next: std_logic;
signal ps2c_filter, ps2d_filter: std_logic_vector(7 downto 0);
signal shift1,shift2: std_logic_vector(10 downto 0);
signal shift1_next,shift2_next: std_logic_vector(10 downto 0);
begin
xkey <= shift1(8 downto 1)&shift2(8 downto 1);
-- filter for PS2 clock and data
filter: process(clk25)
begin
if clk25'event and clk25 = '1' then
ps2c_filter(7) <= PS2C;
ps2c_filter(6 downto 0) <= ps2c_filter(7 downto 1);
ps2d_filter(7) <= PS2D;
ps2d_filter(6 downto 0) <= ps2d_filter(7 downto 1);
PS2Cf <= PS2Cf_next;
PS2Df <= PS2Df_next;
end if;
end process filter;
PS2Cf_next <= '1' when ps2c_filter = X"FF" else
'0' when ps2c_filter = X"00" else
PS2Cf;
PS2Df_next <= '1' when ps2d_filter = X"FF" else
'0' when ps2d_filter = X"00" else
PS2Df;
--Shift used to clock in scan codes from PS2--
shift: process(PS2Cf)
begin
if (PS2Cf'event and PS2Cf = '0') then
shift1 <= shift1_next;
shift2 <= shift2_next;
end if;
end process shift;
Shift1_next <= PS2Df & Shift1(10 downto 1);
Shift2_next <= Shift1(0) & Shift2(10 downto 1);
end keyboard;
You have to change the design to be synchronous specially when using PS2. I recommend you check the clock for the PS2 make sure it is attached to the 25 MHz pin or try use a higher frequency clock and divide it until you get the correct timing. Attached example of dividing a clock by 3, you can change it and use it
Best Wishes,
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity divide_by_3 is
port (
cout :out std_logic; -- Output clock
clk :in std_logic; -- Input clock
reset :in std_logic -- Input reset
);
end entity;
architecture rtl of divide_by_3 is
signal pos_cnt :std_logic_vector (1 downto 0);
signal neg_cnt :std_logic_vector (1 downto 0);
begin
process (clk, reset) begin
if (reset = '1') then
pos_cnt <= (others=>'0');
elsif (rising_edge(clk)) then
if (pos_cnt = 2) then
pos_cnt <= pos_cnt + 1;
end if;
end if;
end process;
process (clk, reset) begin
if (reset = '1') then
neg_cnt <= (others=>'0');
elsif (falling_edge(clk)) then
if (neg_cnt = 2) then
neg_cnt <= neg_cnt + 1;
end if;
end if;
end process;
cout <= '1' when ((pos_cnt /= 2) and (neg_cnt /= 2)) else
'0';
end architecture;
-------------------------------------------------------
-- Testbench to check the divide_by_3 logic
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity div3_tb is
end entity;
architecture test of div3_tb is
signal cout :std_logic;
signal clk :std_logic := '1';
signal reset :std_logic := '1';
component divide_by_3 is
port (
cout :out std_logic;
clk :in std_logic;
reset :in std_logic
);
end component;
begin
-- Generate clock
clk <= not clk after 10 ns;
reset <= '0' after 20 ns;
Inst_div3 : divide_by_3
port map (
cout => cout, -- Output
clk => clk, -- Input
reset => reset -- Iinput
);
end architecture
;
Now that I have managed to shift my text while writing, I want to implement another feature, scrolling the text 1 digit per second. So for example I will will write "STACK" from keyboard, and then when I toggle a pin it will start floating on the seven segment display. I am getting multiple clocks error as I expected. Now, I got over that error with a counter but the text is not scrolling properly, random characters appear on random locations.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;
entity my_shifter is
port(clk : in std_logic;
doShift : in std_logic;--shift mode
Scan_Dav : in std_logic;--from keyboard module, new data
Data_in : in std_logic_vector (7 downto 0);--scancode of the key pressed
O1 : out std_logic_vector(7 downto 0);
O2 : out std_logic_vector(7 downto 0);
O3 : out std_logic_vector(7 downto 0);
O4 : out std_logic_vector(7 downto 0)
);
end my_shifter;
architecture bhv of my_shifter is
signal bytes : std_logic_vector(63 downto 0):=(others => '0');
signal Scan_Dav_Sync: std_logic_vector(1 downto 0):="00";
signal Previous_Scan_Dav: std_logic:='0';
signal shift : std_logic:='0';
signal flag : std_logic:='0';
signal first_letter: std_logic_vector(7 downto 0):="00000000";
begin
process(clk)
variable var:integer range 0 to 50000000 :=0;
begin
if rising_edge(clk) then
if var = 50000000 then
var:=0;
flag<='0';
shift <= '1';
else
flag <= '1';
var:=var+1;
shift <= '0';
end if;
end if;
end process;
process (clk, doShift)
begin
case doShift is
when '0' =>
if rising_edge(clk) then
Scan_Dav_Sync(0) <= Scan_Dav;
Scan_Dav_Sync(1) <= Scan_Dav_Sync(0);
Previous_Scan_Dav <= Scan_Dav_Sync(1);
if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end if;
end if;--till here it works fine.
when '1' => -- this is where it messes up
if (shift = '1' and flag = '0' ) then
first_letter <= bytes(bytes'high downto bytes'high-7);
bytes <= bytes (bytes'high-8 downto 0) & first_letter;
end if;
when others =>--ignore here
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end case;
end process;
O1 <= bytes(31 downto 24);
O2 <= bytes(23 downto 16);
O3 <= bytes(15 downto 8);
O4 <= bytes(7 downto 0);
end bhv;
I wonder how I can overcome this issue? What or where is the error?
Most likely you can get away with this working if you make your second process a sane clocked process.
Something like:
process (clk)
begin
if rising_edge(clk) then
case doShift is
when '0' =>
Scan_Dav_Sync(0) <= Scan_Dav;
Scan_Dav_Sync(1) <= Scan_Dav_Sync(0);
Previous_Scan_Dav <= Scan_Dav_Sync(1);
if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end if;
when '1' =>
if (shift = '1' and flag = '0' ) then
first_letter <= bytes(bytes'high downto bytes'high-7);
bytes <= bytes (bytes'high-8 downto 0) & first_letter;
end if;
when others =>
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end case;
end if;
end process;
I am near to end in my project but stuck at some point. I can not resolve the problem
After deciding VHDL is having a hard time shifting indexes of arrays, I decided to change my shifter module. Now it is properly compiling and the RTL schematic seems true, but unfortunately I used a rather non-innovative way to shift the scancodes.
I defined an 64bit std_logic_vector that can hold up to 8 scancodes, and then parsed the 4 MSBmost bytes of this vector, and directed them to seven segment controller, that muxes the inputs and decides which seven segment will be enabled. I am thinking that I have problems with clock, but seeing nothing on the display makes me think some part of the device is malfunctioning. I am sure my keyboard controller works fine, as I tried it outindividually, shifter looks fine as well( I also tried this one on FPGA but without slowing the clock down, but nevertheless I was able to see the last scancode I entered), I haven't thought of any way/method to try out 7 segment controller, but that seems fine too. I don't know what the problem is, the text is not scrolling :(
Shifter.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;
entity my_shifter is
port(clk : in std_logic;
Scan_Dav : in std_logic;
Data_in : in std_logic_vector (7 downto 0);
O1 : out std_logic_vector(7 downto 0);
O2 : out std_logic_vector(7 downto 0);
O3 : out std_logic_vector(7 downto 0);
O4 : out std_logic_vector(7 downto 0)
);
end my_shifter;
architecture bhv of my_shifter is
signal bytes : std_logic_vector(63 downto 0);
begin
process (clk) begin
if rising_edge(clk) then
if Scan_Dav = '1' then
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end if;
end if;
end process;
O1 <= bytes(63 downto 56);
O2 <= bytes(55 downto 48);
O3 <= bytes(47 downto 40);
O4 <= bytes(39 downto 32);
end bhv;
clkdivide.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clkdivide is
Port (clkin: in std_logic;
clkout:out std_logic );
end clkdivide;
architecture Behavioral of clkdivide is
signal int_clock:std_logic;
begin
clkout<=int_clock;
process(clkin)
variable var:integer range 0 to 12500 :=0;
begin
if (clkin'event and clkin = '1') then
if var = 12500 then
int_clock <= not int_clock;
var:=0;
else
var:=var+1;
end if;
end if;
end process;
end Behavioral;
SevenSegmentControl.vhd:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity SevenSegmentController is
port (
CLK: in std_logic;
DEC1, DEC2, DEC3, DEC4: in std_logic_vector(7 downto 0);
SEGMENTS: out std_logic_vector(6 downto 0);
ANODES: out std_logic_vector(3 downto 0)
);
end SevenSegmentController;
architecture Behavioral of SevenSegmentController is
signal DecoderInput: std_logic_vector(7 downto 0);
signal CurrentDisplay: std_logic_vector(1 downto 0) := "00";
signal Prescaler: std_logic_vector(15 downto 0) := (others => '0');
begin
Multiplex: process(CLK)
begin
if rising_edge(CLK) then
if Prescaler(15) = '0' then
Prescaler <= Prescaler + 1;
else
CurrentDisplay <= CurrentDisplay + 1;
Prescaler <= (others => '0');
end if;
end if;
end process Multiplex;
SevenSegmentDecoder: entity work.SevenSegment_Decoder(Behavioral)
generic map ( INVERT_OUTPUT => '1' )
port map ( number => DecoderInput, segment => SEGMENTS );
DecoderInput <= DEC1 when CurrentDisplay = "00" else
DEC2 when CurrentDisplay = "01" else
DEC3 when CurrentDisplay = "10" else
DEC4 when CurrentDisplay = "11";
ANODES <= "0111" when CurrentDisplay = "00" else
"1011" when CurrentDisplay = "01" else
"1101" when CurrentDisplay = "10" else
"1110" when CurrentDisplay = "11";
end Behavioral;
We have no idea of the interface protocol of SevenSegment_Decoder, but it does look funny that you only have two inputs, but no clock. How does the decoder know when to interpret the signals?
"I haven't thought of any way/method to try out 7 segment controller"
Unless you are using a VERY old version of ISE, certainly older than ISE10, it has a fairly decent simulator (ISIM) built in. (ISIM goes back further than ISE10, but it wasn't really usable and even ISIM 10 had its problems...)
You would save a lot of time if you wrote a simple testbench and unit-tested these modules as you went along.