I need a clarification on SystemVerilog IEEE Std 1800-2012, ports section 23.2.2.3.
The LRM says when the port kind (net type or variable) is omitted on input port, it defaults to net type, but when the input port is of bit data type without specifying the port kind, does it infer to net type according to LRM?
A reply would be highly appreciated!
The port kind defaults to a net and you referenced, but 6.7.1 Net declarations with built-in net types says that net types are restricted to 4-state integral types. So you should get an error if you try to declare input bit instead of input var bit.
Note that earlier versions of the SystemVerilog LRM had the default port kind a variable when specifying a data type without a port kind. Some tools might not generate an error if they are not up to date.
"bit" only specifies the data type, not the net type, of a signal.
When you declare a port as "input bit foo", the tools are supposed to infer net type based on whatever `default_nettype is set to.
A number of verilog style guides have recommended "`default_nettype none" as a poor-mans linting tool to detect typos in net names. This breaks under systemverilog, in so far as it then starts requiring that everything be declared with both a net and a data type, like this:
input wire bit foo
Everybody hates that, so instead:
don't use "`default_nettype none"
use a real linting tool to do linting instead.
Related
Hello I’m new to Verilog and I’ve been confused over this. In some examples the inputs and outputs are declared as wires or regs and on others they are just listed like this:
Module(input a, b, output c)
What is the default data type given to these values?
The default data type for a port in any direction is an unsigned 4-state scalar (1 binary digit). In Verilog, input and inout ports must be and default to the net type wire. output ports also default to wire but can also be specified as a variable reg. (SystemVerilog relaxes some of these rules by allowing input ports to also be declared as variables).
Now that you know what the implicit defaults are, please be a good engineer and never rely on them—be explicit.
I am a beginner in circuit synthesis, and I came across the word net a lot, but I am never able to find its standard definition. It seems to me that it refers to any kind of "black box" where it receives inputs and produce outputs. So it can be a sub circuit inside a big circuit and it can be an array of gates. Is my understanding correct?
No, your understanding is not correct.
Verilog
In Verilog, net has a precise definition:
IEEE 1800-2012 states:
6.5 Nets and variables
There are two main groups of data objects: variables and nets. These two groups differ in the way in which they
are assigned and hold values.
A net can be written by one or more
continuous assignments, by primitive outputs, or through module ports.
The resultant value of multiple drivers is determined by the
resolution function of the net type. A net cannot be procedurally
assigned.
A net can be one of many types, for example: wire, supply0, wand, but by far the most common type is wire.
IEEE 1800-2012 goes on to say:
Variables can be written by one or more procedural statements,
including procedural continuous assignments. The last write determines
the value. Alternatively, variables can be written by one continuous
assignment or one port.
The main difference between the behaviour of a variable and a net is their behaviour when assigned to from more than one place, as highlighted by the bold text in the two quotes:
For a net, if you assign to it from more than one place, its resulting value is determined by a resolution function, which for the built-in net types (wire etc). The behaviour of the resolution function depends on the net type and that is the difference between the net types. So, for example, with a wire, if both 1'b0 and 1'b1 are assigned to it, the resulting value will be 1'bx (unknown) if both assignments assign values with the same strength. The resolution function is intended to model real electronics. (There is also the added complication of user-defined net types and drive strengths, but let's leave those out for this discussion.)
For a variable, if you assign to it from more than one place, its resulting value is determined by whatever value is written last (just like a normal software variable). So, for example, if a 1'b0 is assigned and then a 1'b1 is assigned, the resulting value will be 1'b1 because that value was assigned last. There is no resolution function involved nor any concept of drive strength.
Both nets and variables are used to model combinational logic and sequential logic. There are rules for when you can use a net and when you can use a variable and the choice of which to use is governed by those rules (given in the quotes above). These were strict in verilog, but have been relaxed in System-Verilog to such an extent that, if you are not designing using tri-state logic, you don't need nets in System-Verilog.
VHDL has exactly the same distinction. The VHDL equivalent of a Verilog net is a signal; the VHDL equivalent of a Verilog variable is a variable. The rules about which to use where in VHDL are different, however, and more strict (no surprise there).
Electronics
In electronics a net means a piece of metal through which current flows. In other words, a net is the connection between one place and another. Physically, it could be a PCB track, a cable, a bond wire or a metal connection on an IC. Generally, in digital electronics, it is most like to be a metal connection on an IC.
Synthesis
So, to answer your question, if someone uses the term "net" when talking about the output of a logic synthesiser (the gate-level netlist), they almost certainly mean the second idea: the construct in whatever format that gate-level netlist uses that models the connection between one gate and another. As it is common for synthesisers to output their gate-level netlist as Verilog, those connections between gates are probably modeled using Verilog nets anyway (probably wires).
In a Verilog module, what is the proper terminology for arguments?
What does a variable default to when it's not defined?
A module in Verilog represents hierarchy that is only used for grouping objects by name and replicating those objects. When you run a simulation or synthesize to hardware, that hierarchy gets flattened. Ports of a module join two signal names together, and after flattening, there is only one signal with multiple names. So modules are structurally connected through ports.
The term argument is terminology from software that usually represents a object that gets copied or referenced when you procedurally call a routine like a function or task.
For your second question, if you refer to a variable without defining it, that is usually a compiler error. There is one exception to that for lazy engineers. If you refer to a undefined variable in a port connection, that variable is implicitly declared as a 1-bit wire. If nothing drives that wire, it has the default value 'z which is treated the same as 'x in any expression.
This feature was originally intended for automatically generated gate-level net-lists where every signal is a 1-bit wire, but causes many problems for RTL descriptions. We strongly recommend that use use the compiler directive `default_nettype none to prevent careless typos.
They are called ports . A Verilog module cannot be called like a function, as it is meant to represent a hardware module with input , output , bi-directional pins etc , so it can only be instanced. These instances can be connected to each other again via their ports. These ports bring in and take out data/value/signals into and out of the modules. Hence ports have direction associated with them. Unlike an arguments in a function which only passes on the value when the function is called , once a connection is made to a port ( via a wire/reg (register) / ...) any change to the connected variable is transferred to the module via the port automatically.
link to a module- port explanation.
http://www.asic-world.com/verilog/syntax2.html
Verilog does have functions and tasks which take arguments.
http://www.asic-world.com/verilog/task_func1.html
Uninitialized variables take on unknown value represented by "x" .
There are a few nuances to it
unconnected wire , tri will be tri-state represented by "z"
any 4 state logic - reg , integer , time will default to "x"
real type to 0 .
Please help to understand the following syntax of verilog port definition.
module same_port (.a(i), .b(i));
// Name ’i’ is declared inside themodule as a inout port.
// Names ’a’ and ’b’ are
// defined for port connections.
Is this connection legal?
Yes, this is legal. It looks like you took this example straight from section 23.2.2.1 of the standard (Non-ANSI style port declarations). As it says there you have two ports a and b which are both connected to internal net i. When you instantiate this module you can use named port connections to connect two different things to i:
same_port inst(.a(connection1), .b(connection2));
In the above instantiation, both connection1 and connection2 will be connected to inst.i.
Even though this is legal, I would advise against using it unless you have a good reason to. This is not very commonly used syntax and could cause confusion for someone else looking at your code. The only place I have seen this is in a verilog netlist automatically generated from an schematic.
At the following URL: https://developer.mozilla.org/en/XPCOM_Interface_Reference/nsICacheVisitor is the following code chunk:
boolean visitDevice(in string deviceID, in nsICacheDeviceInfo deviceInfo);
I thought I was dealing with c++, but "in" is not a c++ keyword according to c++ keyword lists i looked up, nor is it a java keyword. So what's it there for and what's it mean?
It means that the parameter is an input parameter, meaning that it will be used but not modified by the function.
The opposite of an in parameter is an out parameter, which means that the parameter is going to be modified, but not explicitly returned. If you were to use an out parameter after a method that uses it, the value is going to (potentially) be different.
As nos points out in the comment, the page you linked to is describing a .idl, or Interface definition language, file. I'm not familiar with the IDL that Mozilla uses (but if you want to learn more, you can read about it here), but I am somewhat familiar with the Object Management Group's IDL, which says that in parameters are call-by-value, out parameters are call-by-result, and inout parameters are call-by-value/result.
The language is Mozilla's Interface Description Language (XPIDL).
The keyword "in" is described here: here
I've seen frameworks/SDKs for C/C++ that define macros to indicate whether a parameter is for input, output or both. I'm guessing that that's what's going on in your example.
For example, the Windows DDK does this for IN OUT and INOUT (if I remember right). When compiling these macros are defined to nothing, they have the potential to be defined to something useful for other tools (like an IDL compiler or a static analysis tool). I;m not sure if they still use these macros in the more recent DDKs.
Microsoft has taken this idea to an extreme with the SAL macros that give a very fine level of control over what behavior is expected for a parameter.