Error: Inconsistent with 'net' object - verilog

Question

I'm getting this error when I'm trying to simulate my testbench on ModelSim. I'm just in the early stage of the testbench, and I'm just adding some values to a variable when this error appears.
I have instantiated the topmodule and created the DUT for it in the testbench. Using the instance I'm going in the hierarchy where I get my desired variable that I want to assign a value.
I have googled for an answer to this question and the only thing I have found is that I cannot make a procedural assignment to a wire. The thing is that that the variable in question is an input, not a wire.
The project I'm working on is based on the openRISC 1200 architecture. I could not find any testbench that worked properly, that's why I'm trying to write my own.
Below is the testbench code:
module testbenchOR (
);
reg cmd;
reg rst;
reg clk;
//----------------------TOP-LEVEL--------------------------------------
wire iwb_cyc_o; // cycle valid output
wire [31:0] iwb_adr_o; // address bus outputs
wire iwb_stb_o; // strobe output
wire iwb_we_o; // indicates write transfer
wire [3:0] iwb_sel_o; // byte select outputs
wire [31:0] iwb_dat_o; // output data bus
wire dwb_cyc_o; // cycle valid output
wire [31:0] dwb_adr_o; // address bus outputs
wire dwb_stb_o; // strobe output
wire dwb_we_o; // indicates write transfer
wire [3:0] dwb_sel_o; // byte select outputs
wire [31:0] dwb_dat_o; // output data bus
wire [3:0] dbg_lss_o; // External Load/Store Unit Status
wire [1:0] dbg_is_o; // External Insn Fetch Status
wire [10:0] dbg_wp_o; // Watchpoints Outputs
wire dbg_bp_o; // Breakpoint Output
wire [31:0] dbg_dat_o; // External Data Output
wire dbg_ack_o; // External Data Acknowledge (not WB compatible)
wire [3:0] pm_clksd_o;
wire pm_dc_gate_o;
wire pm_ic_gate_o;
wire pm_dmmu_gate_o;
wire pm_immu_gate_o;
wire pm_tt_gate_o;
wire pm_cpu_gate_o;
wire pm_wakeup_o;
wire pm_lvolt_o;
reg clk_i;
reg rst_i;
reg [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
reg [19:0] pic_ints_i;
reg iwb_clk_i; // clock input
reg iwb_rst_i; // reset input
reg iwb_ack_i; // normal termination
reg iwb_err_i; // termination w/ error
reg iwb_rty_i; // termination w/ retry
reg [31:0] iwb_dat_i; // input data bus
reg dwb_clk_i; // clock input
reg dwb_rst_i; // reset input
reg dwb_ack_i; // normal termination
reg dwb_err_i; // termination w/ error
reg dwb_rty_i; // termination w/ retry
reg [31:0] dwb_dat_i; // input data bus
reg dbg_stall_i; // External Stall Input
reg dbg_ewt_i; // External Watchpoint Trigger Input
reg dbg_stb_i; // External Address/Data Strobe
reg dbg_we_i; // External Write Enable
reg [31:0] dbg_adr_i; // External Address Input
reg [31:0] dbg_dat_i; // External Data Input
reg pm_cpustall_i;
or1200_top TOP_LEVEL(
.iwb_cyc_o(iwb_cyc_o),
.iwb_adr_o(iwb_adr_o),
.iwb_stb_o(iwb_stb_o),
.iwb_we_o(iwb_we_o),
.iwb_sel_o(iwb_sel_o),
.iwb_dat_o(iwb_dat_o),
.dwb_cyc_o(dwb_cyc_o),
.dwb_adr_o(dwb_adr_o),
.dwb_stb_o(dwb_stb_o),
.dwb_we_o(dwb_we_o),
.dwb_sel_o(dwb_sel_o),
.dwb_dat_o(dwb_dat_o),
.dbg_lss_o(dbg_lss_o),
.dbg_is_o(dbg_is_o),
.dbg_wp_o(dbg_wp_o),
.dbg_bp_o(dbg_bp_o),
.dbg_dat_o(dbg_dat_o),
.dbg_ack_o(dbg_ack_o),
.pm_clksd_o(pm_clksd_o),
.pm_dc_gate_o(pm_dc_gate_o),
.pm_ic_gate_o(pm_ic_gate_o),
.pm_dmmu_gate_o(pm_dmmu_gate_o),
.pm_immu_gate_o(pm_immu_gate_o),
.pm_tt_gate_o(pm_tt_gate_o),
.pm_cpu_gate_o(pm_cpu_gate_o),
.pm_wakeup_o(pm_wakeup_o),
.pm_lvolt_o(pm_lvolt_o),
.clk_i(clk_i),
.rst_i(rst_i),
.clmode_i(clmode_i),
.pic_ints_i(pic_ints_i),
.iwb_clk_i(iwb_clk_i),
.iwb_rst_i(iwb_rst_i),
.iwb_ack_i(iwb_ack_i),
.iwb_err_i(iwb_err_i),
.iwb_rty_i(iwb_rty_i),
.iwb_dat_i(iwb_dat_i),
.dwb_clk_i(dwb_clk_i),
.dwb_rst_i(dwb_rst_i),
.dwb_ack_i(dwb_ack_i),
.dwb_err_i(dwb_err_i),
.dwb_rty_i(dwb_rty_i),
.dwb_dat_i(dwb_dat_i),
.dbg_stall_i(dbg_stall_i),
.dbg_ewt_i(dbg_ewt_i),
.dbg_stb_i(dbg_stb_i),
.dbg_we_i(dbg_we_i),
.dbg_adr_i(dbg_adr_i),
.dbg_dat_i(dbg_dat_i),
.pm_cpustall_i(pm_cpustall_i)
);
initial begin
$display (" --- Start --- ");
clk =0;
rst <= 1;
repeat (1) # (posedge clk);
rst <= 0;
cmd <= 0;
repeat (10) # (posedge clk);
cmd <= 1;
repeat (10) # (posedge clk);
end
// Clock generator
always #10 clk = ~clk;
initial begin
#(posedge clk)
TOP_LEVEL.or1200_cpu.or1200_rf.rf_a.ce_w = 1'b0; //Chip enable input
end
endmodule
The error is as follows:
This or another usage of 'TOP_LEVEL.or1200_cpu.or1200_rf.rf_a.ce_w'
inconsistent with 'net' object.
UPDATE:
The error can be removed by doing the following:
initial begin
#(posedge clk)
force TOP_LEVEL.or1200_cpu.or1200_rf.rf_a.ce_w = 1'b0; //Chip enable input
#500
release TOP_LEVEL.or1200_cpu.or1200_rf.rf_a.ce_w;
end

Answer 1

You may need to use force for an input/wire:
initial begin
#(posedge clk)
force TOP_LEVEL.or1200_cpu.or1200_rf.rf_a.ce_w = 1'b0; //Chip enable input
end
Keep in mind that force will hold that value until you release the signal. Refer to IEEE Std 1800-2012, section "10.6.2 The force and release procedural statements". Also keep in mind that force/release should be used sparingly.