Unresolved reference to 'memory' - verilog

Question

I'm trying to add a mif file in the Test benh and I am getting ERROR's
here i am using the modelsim simulator and i am getting error as
UNRESOLVED REFERENCE TO MEMEORY
Illegal output or inout port connection for port 'dout'.
Error loading design
`timescale 1ns / 1ps
module ESC_tb;
// Internal TB Signal Definition
reg clock;
reg reset;
wire [4:0] pc_out;
wire [7:0] acc_out;
wire [7:0] mdr_out;
// DUT Instantiation
ESC instESC(.clock (clock),
.reset (reset),
.pc_out (pc_out),
.acc_out(acc_out),
.mdr_out(mdr_out)
);
// Initialize block for Clock and Reset
initial
begin : RESET
reset = 0;
#7 reset = 1;
#18 reset = 0;
end
initial
begin : CLOCK
clock = 1;
#5 clock = 0;
forever #(5) clock = ~clock;
end
// Loading Program and Data Memory
initial
begin : MEMLOAD
#5;
**// GETTING ERROR AT THIS POINT**
$readmemh("program.mif", memory);
/66/
$display("Loaded Memory with program.mif file");
end
initial
begin : DUMP_FINISH
$dumpvars;
#1000
$finish(2);
end
endmodule
MEMORY.FILE
module memory (clock, addr, din, we, dout,clear);
// Input/Output Declaration
input clock;
input [4:0] addr;
input [7:0] din;
input we,clear;
output [7:0] dout;
// Signal Type Definition
wire clock;
wire [4:0] addr;
wire [7:0] din;
wire we;
wire [7:0] dout;// Memory Array Declaration of Size 16x256
reg [7:0] mem [0:31];
// Memory Write Operation
always #(posedge clock)
begin
if(we)
mem[addr] <= din;
if(clear)
mem[addr] <= 0;
end
// Memory Read Operation
assign dout = mem[addr];
// End of Module Declaration
endmodule

Answer 1

memory is a module, $readmemh is looking for an array. You need to give the full path from the test bench to mem (within the memory module), or call $readmemh within the memory module.
From TB: $readmemh("program.mif", ESC_tb.instESC./*rest of path*/.mem);
From memory module: initial $readmemh("program.mif", mem);