The code below shows a finite state machine that controls a separate datapath module to find the GCD of two 4-bit numbers. I am currently getting the following errors, and I'm not sure why. Maybe they are due to some syntax I'm not aware of:
ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD123/Controller.v" Line 48: Syntax error near ";".
ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD123/Controller.v" Line 59: Syntax error near ";".
ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD123/Controller.v" Line 62: Syntax error near ";".
The code where the errors are encountered is below:
module Controller(start,reset,x_sel,y_sel,xlty,xgty,xequaly,clk);
input start,clk, reset, xlty, xgty,xequaly;
output x_sel,y_sel;
// Declare state register
reg [1:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
debounce startd(.clock(clk),.noisy(start),.clean(clean_start));
always # (posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (clean_start)
state <= S1;
else
state <= S0;
S1:
x_sel <= 0;
y_sel <= 0;
state <= S2;
S2:
if (xlty)
state <= S3;
else if(xgty)
state <= S4;
else if(xequaly)
state <= S5;
S3:
y_sel <= 1;
state <= S2;
S4:
x_sel <= 1;
state <= S2;
S5:
state <= S0;
endcase
end
endmodule
The lines that have the errors are y_sel <= 0; in the S1 state, state <= S2; in the S4 state and state <= S2; in the S3 state.
You need begin/end keywords around consecutive statements:
module Controller(start,reset,x_sel,y_sel,xlty,xgty,xequaly,clk);
input start,clk, reset, xlty, xgty,xequaly;
output x_sel,y_sel;
// Declare state register
reg [1:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
debounce startd(.clock(clk),.noisy(start),.clean(clean_start));
always # (posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (clean_start)
state <= S1;
else
state <= S0;
S1:
begin
x_sel <= 0;
y_sel <= 0;
state <= S2;
end
S2:
if (xlty)
state <= S3;
else if(xgty)
state <= S4;
else if(xequaly)
state <= S5;
S3:
begin
y_sel <= 1;
state <= S2;
end
S4:
begin
x_sel <= 1;
state <= S2;
end
S5:
state <= S0;
endcase
end
endmodule
Related
module FiniteStateMachine(output reg [2:0] Count, input clock, reset);
reg[2:0] state, next_state;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101, S6 = 3'b110, S7 = 3'b111;
always # (posedge clock, negedge reset)
if(reset==0) state<=S0;
else state <= next_state;
always # (state)
case(state)
S0: begin
Count = S0;
next_state = S1;
end
S1: begin
Count = S1;
next_state = S2;
end
S2: begin
Count = S3;
next_state = S3;
end
S3: begin
Count = S7;
next_state = S4:
end
S4: begin
Count = S6;
next_state = S5;
end
S5: begin
Count = S4;
next_state = S0;
end
endcase
endmodule
Getting the error:
Syntax in assignment statement l-value
I've also tried "<=" instead of "=" for all the assignments in case, but I'm getting the same error.
You used a colon instead of a semicolon. Change:
next_state = S4:
to:
next_state = S4;
I want to build a module based on this state diagram. The code below is the module I wrote and the test bench.When you build this,
you can face this error.
./3bit_c_sdiagram.v:1: syntax error
I give up.
How can I solve this syntax error? and
If my code is far from the solution, how do I code it?
3bit_c_sdiagram.v
module 3bit_c_sdiagram(y_out, clock, reset);
output y_out;
input clock, reset;
reg[2:0] state;
parameter S0=3'b000, S1=3'b001, S2=3'b010, S3=3'b011, S4=3'b100, S5=3'b101,
S6=3'b110, S7=3'b111;
always # (posedge clock, negedge reset)
if(reset == 0) state <= S0; //Initialize to state S0
else case(state)
S0: if(clock) state <= S1; else state <= S0;
S1: if(clock) state <= S2; else state <= S1;
S2: if(clock) state <= S3; else state <= S2;
S3: if(clock) state <= S4; else state <= S3;
S4: if(clock) state <= S5; else state <= S4;
S5: if(clock) state <= S6; else state <= S5;
S6: if(clock) state <= S7; else state <= S6;
S7: if(clock) state <= S0; else state <= S7;
endcase
assign y_out = (state == S7);
endmodule
simulat.v
module simulate;
wire t_y_out;
reg t_reset;
reg t_clock;
3bit_c_sdiagram M1(t_y_out, t_clock, t_reset);
initial #200 $finish;
initial begin
$dumpfile("test.vcd");
$dumpvars(0,simulate);
t_reset = 0;
t_clock = 0;
#5 t_reset = 1;
repeat(16)
#5 t_clock = ~t_clock;
end
endmodule
3bit_c_sdiagram is an illegal identifer (ie name) in Verilog. Verilog names can contain letters, numbers, dollar signs or underscores, but they must start with a letter or an underscore.
As stated in the other solution, your module name cannot start with a number.
I am adding this answer just to outline one thing in your example (even if it is not an answer to your question). In your code, you have:
always # (posedge clock, negedge reset)
if(reset == 0) state <= S0; //Initialize to state S0
else case(state)
S0: if(clock) state <= S1; else state <= S0;
This always# statement will run in two cases:
- when your clock rises
- OR when your reset drops
You first test reset==0, then go into the else statement. Based on what was said before, that else statement will run ONLY when your clock rises (because you know reset != 0).
Bottom line: no need to test for if (clock). You can do the following:
always # (posedge clock, negedge reset)
if(reset == 0) state <= S0; //Initialize to state S0
else case(state)
S0: state <= S1; else state <= S0;
...
The else state <= S0 statements are not needed either, this is what will happen by default (your reg will no change value unless you explicitly change it). But if it helps in clarifying things for you, it doesn't hurt either...
I hope this helps!
So i am currently doing a little project involving a hd44780 display. But since i want to write my own init sequence i decided to use a state machine. I am quite new to FPGAs an their programming coming from a Java background.
This is my State machine Block.
I this state it works and the IDE doesnt show any errors.
always #(posedge reset)
begin
en_timeout <= 2'b00;
timeout <= 14'b00000000000000;
init <= 4'b000;
data <= 8'b00000000;
en <= 1'b1; //active low
rs <= 1'b0;
rw <= 1'b0;
state <= 4'b0000;
next_state <= 4'b0000;
debug <= 1'b0;
end
if(timeout == 0)
begin //Begin of Initiation state machine
case(state)
s0:
begin
end
s1:
begin
end
s2:
begin
end
s3:
begin
end
s4:
begin
end
s5:
begin
end
s6:
begin
end
s7:
begin
end
s8:
begin
end
s9:
begin
end
s10:
begin
end
normal:
begin
end
endcase
end //End of Initiation state machine
But if i add any assignment between the begin and end of one of the states it shows me "Line n: Syntax error near "<="."
for example:
case(state)
s0:
begin
state <= s1;
end
Full code of my DisplayDriver so far:
module DisplayDriver(
output reg [8:0] data,
output reg en,
output reg rs,
output reg rw,
output reg debug,
input clk,
input reset
);
parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8,s9=9,s10=10,normal = 11;
reg [3:0] state; // 4 bit for max 11 combinations s0-s10 and normal
reg [3:0] state; // 4 bit for max 11 combinations s0-s10 and normal [next State]
reg [1:0] en_timeout; // 2 bit for en high to low to high cylce
reg [13:0] timeout; // 14 bit
initial
// begin init
begin
en_timeout <= 2'b00;
timeout <= 14'b00000000000000;
init <= 4'b000;
data <= 8'b00000000;
en <= 1'b1; //active low
rs <= 1'b0;
rw <= 1'b0;
state <= 4'b0000;
next_state <= 4'b0000;
debug <= 1'b0;
end
// end of init
always #(posedge clk)
//begin of everything that needs the clock
begin
if(en_timeout > 0) //begin timeout stack
begin
en_timeout <= en_timeout -1;
en <= ~en;// if en_timeout = 2 -> en = 0; if en_timeout = 1 -> en = 1;
end
else if (timeout > 0) timeout <= timeout -1; //end timeout stack
if(timeout == 0)state <= next_state;
end //end of everything that needs the clock
always #(posedge reset)
begin
en_timeout <= 2'b00;
timeout <= 14'b00000000000000;
init <= 4'b000;
data <= 8'b00000000;
en <= 1'b1; //active low
rs <= 1'b0;
rw <= 1'b0;
state <= 4'b0000;
next_state <= 4'b0000;
debug <= 1'b0;
end
if(timeout == 0)
begin //Begin of Initiation state machine
case(state)
s0:
begin
end
s1:
begin
end
s2:
begin
end
s3:
begin
end
s4:
begin
end
s5:
begin
end
s6:
begin
end
s7:
begin
end
s8:
begin
end
s9:
begin
end
s10:
begin
end
normal:
begin
end
endcase
end //End of Initiation state machine
endmodule
Does anyone have an idea why it behaves this way?
I assume that you are trying to synthesize a register for "state", in which case the update "<=" needs to be inside always (#posedge clk).
I having been trying to implement a simple sequence detector on a Nexys 3 (Spartan 6) board. The code works perfectly on Xilinx simulation but on the hardware, it doesn't work. Since I am new to FPGA implementation I couldn't solve this issue.
I dont know what changes I should make for the code to work in hardware.
It would be great if someone could help me..
And this is the code
module sequence( in, clock,reset,test);
input in;
input reset;
output reg test=0;
reg [3:0] state=0, next=0 ;
input clock;
always#( posedge clock)
begin
if(reset==1)
begin
state= 0;
end
else
begin
state=next;
end
end
always #*
begin
if(reset == 1)
begin
next=0;
test=0;
end
else
begin
case ( state )
'd0 : begin
if ( in==1)
begin
next=state+1;
end
else
next=next;
end
'd1 : begin
if ( in==1)
begin
next=state+1;
end
else
next=0;
end
'd2 : begin
if ( in==1)
begin
next=state+1;
end
else
next=0;
end
'd3 : begin
if ( in==1)
begin
next=state+1;
end
else
next=0;
end
'd4 : begin
if ( in==1)
begin
next=state+1;
test=1;
end
else
next=0;
end
default : begin
next=0;
test=0;
end
endcase
end
end
endmodule
I would change the beginning of your always block to:
always #*
begin
next = state;
test = 0;
case (state)
'd0 :
begin
if ( in==1)
next=state+1;
end
...
Setting a default assignment to all values in the state machine eliminates the possibility of creating an implicit latch. Your "next = next" statement shouldn't have any effect but might be creating latch (should probably be "next = state').
Also test is not assigned in every branch and has no default, so it will also create a latch.
The problems that I found in your Verilog code is given below.
Output variable test must be assigned in every case statement branches, else unwanted latches will form.
Use nonblocking assignments when you are specifying sequential circuit.
Try to code your sequence detector as below.
//sequence detector 101101
module fsm (rst,in1,clk,out1);
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;
input rst,in1,clk;
output reg out1;
reg [2:0] state;
always #(posedge clk)
if (rst)
begin
state <= s0;
out1 <= 0 ;
end
else
case(state)
s0 : if (in1) begin state <= s1; out1 <= 0 ; end
else begin state <= s0; out1 <= 0 ; end
s1 : if (in1) begin state <= s0; out1 <= 0 ; end
else begin state <= s2; out1 <= 0 ; end
s2 : if (in1) begin state <= s3; out1 <= 0 ; end
else begin state <= s0; out1 <= 0 ; end
s3 : if (in1) begin state <= s4; out1 <= 0 ; end
else begin state <= s2; out1 <= 0 ; end
s4 : if (in1) begin state <= s1; out1 <= 0 ; end
else begin state <= s5; out1 <= 0 ; end
s5 : if (in1) begin state <= s1; out1 <= 1 ; end
else begin state <= s0; out1 <= 0 ; end
default: if (in1) begin state <= s0; out1 <= 0 ; end
else begin state <= s0; out1 <= 0 ; end
endcase
endmodule
I am trying to design a fsm for showing rotational which runs the 4-digit 7-segment LED display unit, to cause a rotating pattern of circulating squares in clockwise or counterclockwise. I am trying to fix the syntax errors in my case block but I am in verilog coding and I cannot find my mistake. Here is the code:
module fsm( EN, CW, clk, AN1,AN2,AN3,AN4, leds );
//inputs and outputs
input EN, CW, clk;
output AN1,AN2,AN3,AN4;
output reg leds[6:0];
//state register and parameters
reg state[3:0];
parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter s4 = 3'b100;
parameter s5 = 3'b101;
parameter s6 = 3'b110;
parameter s7 = 3'b111;
//states and outputs according to the states
always # (posedge clk)
begin
if (EN == 1)
begin
case(state)
s0: leds<=7'b1100011; if(CW)begin state <= s1; end else begin state <= s7; end
s1: leds<=7'b1100011; if(CW)begin state <= s2; end else begin state <= s0; end
s2: leds<=7'b1100011; if(CW)begin state <= s3; end else begin state <= s1; end
s3: leds<=7'b1100011; if(CW)begin state <= s4; end else begin state <= s2; end
s4: leds<=7'b1011100; if(CW)begin state <= s5; end else begin state <= s3; end
s5: leds<=7'b1011100; if(CW)begin state <= s6; end else begin state <= s4; end
s6: leds<=7'b1011100; if(CW)begin state <= s7; end else begin state <= s5; end
s7: leds<=7'b1011100; if(CW)begin state <= s0; end else begin state <= s6; end
endcase
end
end
//output logic
assign AN1 = ~((state == s0) | (state == s7));
assign AN2 = ~((state == s1) | (state == s6));
assign AN3 = ~((state == s2) | (state == s5));
assign AN4 = ~((state == s3) | (state == s4));
endmodule
A few things.
You should declare your vector signals like this:
output reg [6:0] leds;
//state register and parameters
reg [3:0] state;
And, you need to wrap each case item with a begin/end. I also spread the statements across a few lines, which might make it more readable:
s0: begin
leds <= 7'b1100011;
if (CW) begin
state <= s1;
end else begin
state <= s7;
end
end
Or, you could replace the if/else with a ternary:
s0: begin
leds <= 7'b1100011;
state <= (CW) ? s1 : s7;
end