VHDL - ModelSim testbench simulation freezes when sending "run" - io

Question

I have a problem regarding a testbench I am developing for an hardware butterfly algorithm for calculating the Fourier transform.
What I'm attempting to do is reading a series of input data files (32-bit vectors) and writing the output in some other output files.
The input files are Ar.txt, Ai.txt, Br.txt, Bi.txt, Wr.txt and Wi.txt.
The output files are Ar_OUT_TB.txt, Ai_OUT_TB.txt, Br_OUT_TB.txt, Bi_OUT_TB.txt.
But when I try to simulate with ModelSim, the program simply freezes: I can still do some stuff, like opening another project/file etc., but there's no waveform showing, and also the command line is missing. I also tried to simulate an older VHDL project of mine and it did simulate, so I guess the problem is within this code.
These are the main processes (EDIT: I'm also adding the rest of the code, for understanding):
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE STD.TEXTIO.ALL;
ENTITY BUTTERFLY_TESTBENCH IS
END BUTTERFLY_TESTBENCH;
ARCHITECTURE DEVICE OF BUTTERFLY_TESTBENCH IS
COMPONENT progetto_butterfly
GENERIC(N_IN, N_OUT: INTEGER := 32;
N_BUSES: INTEGER := 63);
PORT(START, CLK, MAIN_RST_N: IN STD_LOGIC;
DATA_IN, Wr_IN, Wi_IN: IN SIGNED(N_IN-1 DOWNTO 0);
DATA_OUT: OUT SIGNED(N_IN-1 DOWNTO 0);
DONE: OUT STD_LOGIC);
END COMPONENT;
CONSTANT N_IN: INTEGER := 32;
CONSTANT N_OUT: INTEGER := 32;
SIGNAL TEST_DATA_IN, TEST_Wr_IN, TEST_Wi_IN: SIGNED(N_IN-1 DOWNTO 0);
SIGNAL TEST_OUTPUT: SIGNED(N_OUT-1 DOWNTO 0);
SIGNAL CLK: STD_LOGIC;
SIGNAL TEST_START, TEST_RST, TEST_DONE: STD_LOGIC;
FILE Ar_IN_FILE: TEXT OPEN READ_MODE IS "Ar.txt";
FILE Ai_IN_FILE: TEXT OPEN READ_MODE IS "Ai.txt";
FILE Br_IN_FILE: TEXT OPEN READ_MODE IS "Br.txt";
FILE Bi_IN_FILE: TEXT OPEN READ_MODE IS "Bi.txt";
FILE WR_FILE: TEXT OPEN READ_MODE IS "Wr.txt";
FILE WI_FILE: TEXT OPEN READ_MODE IS "Wi.txt";
FILE Ar_OUT: TEXT OPEN WRITE_MODE IS "Ar_OUT_TB.txt";
FILE Ai_OUT: TEXT OPEN WRITE_MODE IS "Ai_OUT_TB.txt";
FILE Br_OUT: TEXT OPEN WRITE_MODE IS "Br_OUT_TB.txt";
FILE Bi_OUT: TEXT OPEN WRITE_MODE IS "Bi_OUT_TB.txt";
BEGIN
BUTTERFLY_TEST_COMPONENT: progetto_butterfly PORT MAP(START => TEST_START, CLK => CLK, MAIN_RST_N => TEST_RST,
DATA_IN => TEST_DATA_IN, Wr_IN => TEST_Wr_IN, Wi_IN => TEST_Wi_IN,
DATA_OUT => TEST_OUTPUT, DONE => TEST_DONE);``
DATA_IN_PROCESS: PROCESS
VARIABLE DATA_BUFFER: LINE;
VARIABLE DATA_STIMULUS: BIT_VECTOR(N_IN-1 DOWNTO 0);
BEGIN
IF NOT (ENDFILE(Br_IN_FILE)) THEN
IF(TEST_START = '1' AND TEST_RST = '1') THEN
READLINE(Br_IN_FILE,DATA_BUFFER);
READ(DATA_BUFFER,DATA_STIMULUS);
TEST_DATA_IN <= SIGNED(TO_STDLOGICVECTOR(DATA_STIMULUS));
WAIT UNTIL CLK'EVENT AND CLK = '1';
READLINE(Bi_IN_FILE,DATA_BUFFER);
READ(DATA_BUFFER,DATA_STIMULUS);
TEST_DATA_IN <= SIGNED(TO_STDLOGICVECTOR(DATA_STIMULUS));
WAIT UNTIL RISING_EDGE(CLK);
READLINE(Ar_IN_FILE,DATA_BUFFER);
READ(DATA_BUFFER,DATA_STIMULUS);
TEST_DATA_IN <= SIGNED(TO_STDLOGICVECTOR(DATA_STIMULUS));
WAIT UNTIL RISING_EDGE(CLK);
READLINE(Ai_IN_FILE,DATA_BUFFER);
READ(DATA_BUFFER,DATA_STIMULUS);
TEST_DATA_IN <= SIGNED(TO_STDLOGICVECTOR(DATA_STIMULUS));
WAIT FOR 12 ns;
ELSE
TEST_DATA_IN <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
WR_PROCESS: PROCESS
VARIABLE wr_buf: LINE;
VARIABLE WR_STIMULUS: BIT_VECTOR(N_IN-1 DOWNTO 0);
BEGIN
WHILE NOT (ENDFILE(WR_FILE)) LOOP
IF(TEST_START = '1' AND TEST_RST = '1') THEN
READLINE(WR_FILE,wr_buf);
READ(wr_buf,WR_STIMULUS);
TEST_Wr_IN <= SIGNED(TO_STDLOGICVECTOR(WR_STIMULUS));
WAIT FOR 20 ns;
END IF;
END LOOP;
END PROCESS;
WRITING_PROCESS: PROCESS
VARIABLE STRING_LINE: STRING(N_OUT DOWNTO 1);
VARIABLE OUT_LINE: LINE;
VARIABLE I: INTEGER;
BEGIN
WAIT FOR 12 ns;
WHILE (TEST_START = '1' AND TEST_RST = '1') LOOP
FOR I IN N_OUT-1 DOWNTO 0 LOOP
IF(TEST_OUTPUT(I) = '0') THEN
STRING_LINE(I+1) := '0';
ELSE
STRING_LINE(I+1) := '1';
END IF;
END LOOP;
WRITE(OUT_LINE,STRING_LINE);
WRITELINE(Br_OUT,OUT_LINE);
WAIT UNTIL RISING_EDGE(CLK);
FOR I IN N_OUT-1 DOWNTO 0 LOOP
IF(TEST_OUTPUT(I) = '0') THEN
STRING_LINE(I+1) := '0';
ELSE
STRING_LINE(I+1) := '1';
END IF;
END LOOP;
WRITE(OUT_LINE,STRING_LINE);
WRITELINE(Bi_OUT,OUT_LINE);
WAIT UNTIL RISING_EDGE(CLK);
FOR I IN N_OUT-1 DOWNTO 0 LOOP
IF(TEST_OUTPUT(I) = '0') THEN
STRING_LINE(I+1) := '0';
ELSE
STRING_LINE(I+1) := '1';
END IF;
END LOOP;
WRITE(OUT_LINE,STRING_LINE);
WRITELINE(Ar_OUT,OUT_LINE);
WAIT UNTIL RISING_EDGE(CLK);
FOR I IN N_OUT-1 DOWNTO 0 LOOP
IF(TEST_OUTPUT(I) = '0') THEN
STRING_LINE(I+1) := '0';
ELSE
STRING_LINE(I+1) := '1';
END IF;
END LOOP;
WRITE(OUT_LINE,STRING_LINE);
WRITELINE(Ai_OUT,OUT_LINE);
END LOOP;
END PROCESS;
CLK_PROCESS: PROCESS
BEGIN
CLK <= '1';
WAIT FOR 2 ns;
CLK <= '0';
WAIT FOR 2 ns;
END PROCESS;
TEST_RST <= '0', '1' AFTER 2 ns;
TEST_START <= '0', '1' AFTER 3 ns;
END ARCHITECTURE;
Is something done wrong? I can't see what I'm missing.

Answer 1

Your DATA_IN_PROCESS process is an infinite loop. As long as as the condition TEST_START = '1' AND TEST_RST = '1' is not met, the process keeps on running, without incrementing simulated time. It eats up simulator time and simuated time does not increase.
Solve this by adding WAIT UNTIL RISING_EDGE(CLK); in the else clause.
Other problems with your code are listed here: http://www.sigasi.com/vhdl-code-check?ID=27869561

Answer 2

Your processes either need a sensitivity list or a WAIT statement.

Answer 3

After building an MVCe from your example I found that it appears an input file you're reading is too short, revealing faults in two of your processes (data_in_process and wr_process).
library ieee;
use std.textio.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sometb is
end entity;
architecture foo of sometb is
constant n_in: integer := 8;
signal test_start: std_logic := '1';
signal test_rst: std_logic := '1';
file br_in_file: text open READ_MODE is "Br.txt";
signal test_data_in: signed(n_in - 1 downto 0);
signal clk: std_logic := '0';
file bi_in_file: text open READ_MODE is "Bi.txt";
file ar_in_file: text open READ_MODE is "Ar.txt";
file ai_in_file: text open READ_MODE is "Ai.txt";
file wr_file: text open READ_MODE is "Wr.txt";
signal test_wr_in: signed(n_in - 1 downto 0);
constant n_out: integer:= 8;
signal test_output: std_logic_vector(n_out - 1 downto 0);
file br_out: text open WRITE_MODE is "Br_OUT_TB.txt";
file bi_out: text open WRITE_MODE is "Bi_OUT_TB.txt";
file ar_out: text open WRITE_MODE is "Ar_OUT_TB.txt";
file ai_out: text open WRITE_MODE is "Bi_OUT_TB.txt";
begin
CLOCK:
process
begin
wait for 6 ns;
clk <= not clk;
end process;
data_in_process:
process
variable data_buffer: line;
variable data_stimulus: bit_vector(n_in-1 downto 0);
begin
if not endfile(br_in_file) then
if test_start = '1' and test_rst = '1' then
readline(br_in_file,data_buffer);
read(data_buffer,data_stimulus);
test_data_in <= signed(to_stdlogicvector(data_stimulus));
wait until clk'event and clk = '1';
readline(bi_in_file,data_buffer);
read(data_buffer,data_stimulus);
test_data_in <= signed(to_stdlogicvector(data_stimulus));
wait until rising_edge(clk);
readline(ar_in_file,data_buffer);
read(data_buffer,data_stimulus);
test_data_in <= signed(to_stdlogicvector(data_stimulus));
wait until rising_edge(clk);
readline(ai_in_file,data_buffer);
read(data_buffer,data_stimulus);
test_data_in <= signed(to_stdlogicvector(data_stimulus));
wait for 12 ns;
else
test_data_in <= (others => '0');
end if;
end if;
wait until rising_edge(clk); -- added for endfile
end process;
wr_process:
process
variable wr_buf: line;
variable wr_stimulus: bit_vector(n_in-1 downto 0);
begin
while not endfile(wr_file) loop
if test_start = '1' and test_rst = '1' then
readline(wr_file,wr_buf);
read(wr_buf,wr_stimulus);
test_wr_in <= signed(to_stdlogicvector(wr_stimulus));
wait for 20 ns;
end if;
end loop;
wait for 20 ns; -- added for when endfile(wr_file) is TRUE.
end process;
writing_process:
process
variable string_line: string(n_out downto 1);
variable out_line: line;
-- variable i: integer; -- the following are not my i
begin
wait for 12 ns;
while test_start = '1' and test_rst = '1' loop
for i in test_output'range loop -- n_out-1 downto 0 loop
if test_output(i) = '0' then
string_line(i + 1) := '0';
else
string_line(i + 1) := '1';
end if;
end loop;
write(out_line, string_line);
writeline(br_out, out_line);
wait until rising_edge(clk);
for i in test_output'range loop -- n_out-1 downto 0 loop
if test_output(i) = '0' then
string_line(i + 1) := '0';
else
string_line(i + 1) := '1';
end if;
end loop;
write(out_line,string_line);
writeline(bi_out,out_line);
wait until rising_edge(clk);
for i in test_output'range loop -- n_out-1 downto 0 loop
if test_output(i) = '0' then
string_line(i+1) := '0';
else
string_line(i+1) := '1';
end if;
end loop;
write(out_line,string_line);
writeline(ar_out,out_line);
wait until rising_edge(clk);
for i in test_output'range loop -- n_out-1 downto 0 loop
if test_output(i) = '0' then
string_line(i+1) := '0';
else
string_line(i+1) := '1';
end if;
end loop;
write(out_line,string_line);
writeline(ai_out,out_line);
end loop;
end process;
end architecture;
I added
wait until rising_edge(clk); -- added for endfile
before the end of the process in data_in_process, otherwise it would loop without suspending if END_FILE(br_in_file) is TRUE. (And you should really have a test or test that covers all your inputs).
I added
wait for 20 ns; -- added for when endfile(wr_file) is TRUE.
to wr_process for the same reason.
The changes to writing_process were used to discover a working range for the test_output signal. Note the the process declarative item for variable i can be removed, it's not used. (The i there is not the i in the loop constants).
I found the problems with the input files by in a UNIX environment (OS X) touching the input files which creates them with a zero length (after insuring my VHDL simulator would complain if they don't exist).