verilog generate instances from another module in always #(posedge clk) - verilog

Question

module save_random (clk,in,out);
parameter size=10;
parameter k=10;
input clk;
input [k-1:0] in;
output [k-1:0]out;
wire [size:0] cout;
genvar i;
generate
for(i=0;i<size;i=i+1)
begin: level1
always#(posedge clk) begin
random ins(clk,in[i],cout[i+1]);//generte 10 instances from module random to save it //in registers
end
end
endgenerate
assign cout[0]=in[0];
assign out=cout[k];
endmodule
I am just starting to learn verilog,
i have a task to write synthesis code that generate 10 random values and save each value in register or Dflipflop or sth like this.
The first(save_random) module that generate 10 instances from module random(the 2nd one) and connected ..but still have error when I am using clk input with generate i..
module random(clk,d,cout);
parameter size=8;
input [size-1:0] d;
input clk;
output [size-1:0]cout;
reg [size-1:0]cout;
integer i;
always#(posedge clk)
begin
cout<=d;
end
endmodule

Answer 1

You cannot instantiate modules inside an always block. As you have a module random which is a register of size size, you only need to instantiate that module inside your generate if you need more than one:
genvar i;
generate begin
for(i=0;i<size;i=i+1) begin: level1
random ins(clk,in[i],cout[i+1]);
end
end
However, note that in[i] and cout[i+1] are not an 8-bit values. So if you want to use the full 8-bit register, you need to declare them to be 10 (or 11 for cout) 8-bit vectors:
input [7:0] in [9:0];
wire [7:0] cout [10:0];
This tutorial might give you a better idea how generate blocks work: https://www.youtube.com/watch?v=5CKfP4n9ge0