I want to make a module in Verilog which must get a 32 bit wide register variable in port. This variable will be used to count the clock cycle. Then this module will be instantiated in another module. For example: when I fix the value of counter this module must start count from that value.
When I simulate this code I get an error:
Non-net port count cannot be of mode input
module case_1( input clk , input [31:0] counter);
reg [31:0] counter;
always # (posedge clk)
begin
counter <=counter +1
end
endmodule
module counter (input clk , input [31:0] counter )
reg [31:0] counter;
case_1 h1 ( .clk(clk) , .counter(counter) )
endmodule
If a module is an input then you can not drive a value on to it. Driving a value on to an input does not make sense. It needs to be an output.
It think there might be some confusion over the reg and wire types in verilog. These types do not cross module interfaces. a lower (sub) module drives its output as a reg type. the next level up a wire is connected to the port.
From your example a clock received by counter which uses sub module case_1 to implement the counter. Counter value is then driven (first as a reg) then at the top level as a wire.
module case_1(
input clk ,
output reg [31:0] counter
);
initial begin
counter = 'b0;
end
always # (posedge clk) begin
counter <=counter +1;
end
endmodule
module counter (input clk , output wire [31:0] counter );
case_1 h1 ( .clk(clk) , . counter(counter) );
endmodule
Example on EDA Playground.
Related
Hey guys so I written two Verilog modules, one is a state machine and the other is a counter that generates a pulse every half second for the machine to count.I tried to make a a top level design that would instantiate both modules, however when running a test bench, my state outputs would always equal to 'xx'. Any advice or help please?
COUNTER/PULSE:
module pulseit(clk, reset, pulse);
input clk, reset;
output pulse;
reg [25:0] count;
wire pulse;
always # (posedge clk, posedge reset)
if (reset) count <= 26'b0; else
if (pulse) count <= 26'b0; else
count <= count + 26'b1;
endmodule
STATE MACHINE:
module sm(clk, reset, in, state, pulse);
input clk, reset, in, pulse;
output [1:0] state;
reg [1:0] state, nstate;
always # (posedge clk, posedge reset)
if (reset) state <= 2'b0;
else state <= nstate;
always # (*)
begin
nstate = state;
if (pulse)
begin
case(state)
2'b00: nstate = (in)? 2'b01:2'b11;
2'b01: nstate = (in)? 2'b10:2'b00;
2'b10: nstate = (in)? 2'b11:2'b01;
2'b11: nstate = (in)? 2'b00:2'b10;
endcase
end
end
endmodule
TOPLEVEL:
module topLevel(clk, rst, in, state);
input clk, rst, in;
output [1:0] state;
reg [1:0] state;
wire y;
pulseit pull (.clk(clk), .reset(rst), .pulse(y));
sm machine (.clk(clk), .reset(rst), .in(in), .state(state), .pulse(y));
endmodule
While writing a module, it is a good practice for designer to ensure that all the ports must be driven from module. There may be intentional some left-outs of connection, but the major ports must be connected.
Here wire y is connected as an output pulse of pulseit module. But the output pulse is never driven. The pulseit module just increments count and that too it is dependent on pulse signal. Also the FSM module entirely depends on the pulse signal it gets as an input.
pulse needs to be driven by some logic inside pulseit module. I modified the pulseit module as follows and it works fine now:
module pulseit(clk, reset, pulse);
input clk, reset;
output pulse;
reg [25:0] count;
wire pulse;
always # (posedge clk, posedge reset)
if (reset) count <= 26'b0; else
if (pulse) count <= 26'b0; else
count <= count + 26'b1;
// Let's say pulse goes HIGH when 26th bit of count goes HIGH.
assign pulse = count[25]; // NEED TO DRIVE PULSE
endmodule
I have created a testbench for the above design at EDAPlayground for your reference. Some basic info about Verilog/SV modules can be found at this link and this link.
Note : When assigning, Array index must be in range of index to not overflow.
I'm totally new to Verilog programming and I do not understand where to initialize reg variables?
Let's have a look at the following snippets:
Edit:
Warning at synthesize
module test (
output LED0
);
reg led = 1'b1;
assign LED0 = led;
endmodule
or
module test (
output LED0
);
reg led;
initial begin
reg led <= 1'b1;
end
assign LED0 = led;
endmodule
Give me: Using initial value of led since it is never assigned at the line: reg led = 1'b1;
Are reg types only assigned in always# block?
Another example:
module fourBitCounter
(input clk,
output [3:0]counter
);
wire clk;
initial begin
reg[3:0] counter = 4'b1;
end
always# (posedge clk) begin
if(counter > 15)
counter <= 0;
else
counter <= counter + 1;
end endmodule
Here the reg has an initial value of 0 but I've set it before to 1... What's wrong? Thank you!
Are reg types only assigned in always# block?
No, reg types can be assigned in always blocks and initial blocks (plus task and function but I'll skip them in the scope of this question)
For your fourBitCounter, the reg[3:0] counter declared in the initial block creates a local variable also called counter that is only accessible within the scope of the block it was created in. You need to remove the reg[3:0] in the initial block so that the assignment get applied the the intended counter. But it will still not work because you declared counter as an inferred wire type and always/initial blocks cannot assign wires.
counter was declared as an output of a 4-bit inferred wire (output [3:0] counter is synonyms to output wire [3:0] counter). Since counter is assigned in an always block and initial block it needs to be a reg type. Therefore it should be declared as output reg [3:0] counter.
Also, you declared clk as in input and as a local wire, it cannot be both. Ports can be accessed locally, there is no reason to re-declare them as local nets.
FYI: for a 4-bit value, 15+1 equals 0 because there is nothing to store the MSB.
module fourBitCounter (
input clk,
output reg [3:0] counter // 'output reg', not 'output'
);
//wire clk; // do not do this, clk is an input
initial begin
counter = 4'b1; // no 'reg' here
end
always #(posedge clk) begin
if(counter > 15) // this will never evaluate as true with counter declared as 4-bit
counter <= 0;
else
counter <= counter + 1;
end
endmodule
For Verilog, assign statements can only be applied on net types (e.g. wire). This is legal:
module test ( output LED0 ); // LED0 is an inferred wire
assign LED0 = 1'b1;
endmodule
This is illegal:
module test ( output reg LED0 ); // Explicit reg
assign LED0 = 1'b1; // illegal, assign on a reg
endmodule
From your first code sample:
reg led; // <-- This declares one register called "led"
initial begin
reg led <= 1'b1; // <-- This declares a *separate* register called "led"
end // which is only valid in the initial block
The same issue exists in your second sample; you're declaring a separate register in the initial block. Don't use the keywords reg or wire if you're just trying to assign a value.
I want to make Frequency Divider with Counter and MUX.
I make 3 module for project
// 4-bit Counter
module Counter (input clk, input reset, output reg[3:0] out);
always#(posedge clk or posedge reset)
begin
if(reset)
out = 4'b0000;
else
begin
if(clk)
if(out < 4'b1111)
out = out + 4'b0001;
else
out = 4'b0000;
end
end
endmodule
//module 4by1 Mux
module Mux (input [3:0] muxin , input [1:0] sel, output reg muxout);
function _4by1mux;
input [3:0] muxin;
input [1:0] sel;
case (sel)
2'b00 : _4by1mux = muxin[0];
2'b01 : _4by1mux = muxin[1];
2'b10 : _4by1mux = muxin[2];
2'b11 : _4by1mux = muxin[3];
endcase
endfunction
assign muxout = _4by1mux(muxin, sel);
endmodule
//module freqDivider
module freqDivider(input clk, input reset, input [1:0] sel, output reg muxout);
wire [3:0]counterbus;
Counter ct1 (clk, reset, counterbus);
Mux mux1 (counterbus, sel, muxout);
endmodule
module freqDivider is top, and I call module Counter and Mux
but module Mux has problem with
Error (10219): Verilog HDL Continuous Assignment error at Mux.v(19):
object "muxout" on left-hand side of assignment must have a net type
this error
ps. input sel will be changed by time
The error is a result of the muxout output having type reg instead of type wire. In verilog, lines can have two overarching types, either nets (like wire type) or variables (like reg types). To assign values/logic to net types, you need to use assign statements and not always blocks. To assign values/logic to variable types, you can only use always blocks and not assign statements. So, you can either make your assign in the Mux module an always block or, for an easier solution, don't make the muxout output a reg, just leave out the reg keyword and it will be a wire.
Error is that you have declared mux_out as reg type, instead of wire type. Default type of any port is wire. You are doing continuous assignment on that net through assign keyword. And on reg type nets, assignment can only be done inside procedural block (initial, always).
Change to mux_out from output reg to output only.
I am attempting to use an FPGA as a shift register to some LEDs with pwm, but ran into an error while trying to assign a reg containing the value shifted in to an output variable. When I upload it to the FPGA(i'm using the mojo by embedded micro), it does nothing. when I use the simulator, it reports that all of the output variables are never assigned and have the value of X, while all the other variables inside of the module work just fine. here is my code for the shifting module:
module shifting(
input clk,
input shiftingpin,//data to be shifted in
input rst,
output done,
output [3:0]data//pwm compare value output
);
reg [2: 0] ctr_d, ctr_q;
reg don;
reg [3:0]datas;
always #(*) begin
if(ctr_q == 3'b100) begin
ctr_d[2:0] = 3'b0;
don = 1'b1;
end else begin
ctr_d = ctr_q + 1'b1;
don = 1'b0;
end
end
always #(posedge clk) begin
datas[ctr_q] = shiftingpin;// assign value to the output
if (rst) begin
ctr_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
end
end
assign data = datas;
assign done = don;
endmodule
done tells the containing module when to update and assign the value to pwm.
If I understood the question correctly you have a syntax error when trying to drive ports from within always blocks.
When declaring ports they are typically wire by default which can only be driven by ports or assign. Resulting in the code below
module shifting(
input clk,
input shiftingpin,
input rst,
output done,
output [3:0] data
);
reg don;
reg [3:0] datas;
assign done = don;
assign data = datas;
Solution
The solution is to define ports as reg, logic is preferred if you can support System Verilog.
logic will effectively switch between wire and reg as required to make refactoring code easier.
module shifting(
input clk,
input shiftingpin,
input rst,
output reg done,
output reg [3:0] data
);
always #(posedge clk) begin
data[ctr_q] <= shiftingpin; // <-- data port used directly
//...
NB: shift registers can be done with just
always #(posedge clk) begin
datas[3:0] <= {datas[2:0], shiftingpin};
I'm an FPGA noob trying to learn Verilog. How can I "assign" a value to a reg in an always block, either as an initial value, or as a constant. I'm trying to do something like this in the code below. I get an error because the 8 bit constant doesn't count as input. I also don't want to trigger the always off of a clock. I just want to assign a register to a specific value. As I want it to be synthesisable I can't use an initial block. Thanks a lot.
module top
(
input wire clk,
output wire [7:0] led
);
reg [7:0] data_reg ;
always #*
begin
data_reg = 8'b10101011;
end
assign led = data_reg;
endmodule
You can combine the register declaration with initialization.
reg [7:0] data_reg = 8'b10101011;
Or you can use an initial block
reg [7:0] data_reg;
initial data_reg = 8'b10101011;
You should use what your FPGA documentation recommends. There is no portable way to initialize register values other than using a reset net. This has a hardware cost associated with it on most synthesis targets.
The other answers are all good. For Xilinx FPGA designs, it is best not to use global reset lines, and use initial blocks for reset conditions for most logic. Here is the white paper from Ken Chapman (Xilinx FPGA guru)
http://japan.xilinx.com/support/documentation/white_papers/wp272.pdf
The always #* would never trigger as no Right hand arguments change. Why not use a wire with assign?
module top (
input wire clk,
output wire [7:0] led
);
wire [7:0] data_reg ;
assign data_reg = 8'b10101011;
assign led = data_reg;
endmodule
If you actually want a flop where you can change the value, the default would be in the reset clause.
module top
(
input clk,
input rst_n,
input [7:0] data,
output [7:0] led
);
reg [7:0] data_reg ;
always #(posedge clk or negedge rst_n) begin
if (!rst_n)
data_reg <= 8'b10101011;
else
data_reg <= data ;
end
assign led = data_reg;
endmodule
Hope this helps
When a chip gets power all of it's registers contain random values. It's not possible to have an an initial value. It will always be random.
This is why we have reset signals, to reset registers to a known value. The reset is controlled by something off chip, and we write our code to use it.
always #(posedge clk) begin
if (reset == 1) begin // For an active high reset
data_reg = 8'b10101011;
end else begin
data_reg = next_data_reg;
end
end