I want to write code in Verilog for a Ring Oscillator.
Here is my code:
module RingOsci(enable, w1, w2, w3);
input enable;
output w1, w2, w3;
wire w4;
and (w4, enable, w3);
not #2(w2, w1);
not #2(w3, w2);
not #2(w1, w4);
endmodule
But, W_i is always Z.
Here is my test bench:
module RingOsciTB();
reg en;
wire out1, out2, out3;
initial begin
en = 1'b0;
#20
en = 1'b1;
end
endmodule
How can I change the Z value and enable the Oscillator?
You need to add an instance of your design module in your testbench. For example:
module RingOsciTB();
reg en;
wire out1, out2, out3;
RingOsci dut (
// Inputs:
.enable (en),
// Outputs:
.w1 (out1),
.w2 (out2),
.w3 (out3)
);
initial begin
en = 1'b0;
#20
en = 1'b1;
end
endmodule
Related
I realize that this may be very easy to fix but I can't find a way to make it work.
My question is how can I get visual signals of CE2 and CEO in this case? I know by looking on RTL Scheme CE2 and CEO isn't connected to pins. And I just can't connect them.
CE2 should be ON when first counter reach 9 but on waveform its always as X. And CEO should be ON when Q is 9 but on waveform its always Z.
This circuit is just for self learning.
Testbench
Circuit Scheme
TOP MODULE:
`timescale 1ns / 1ps
module top(
input CLK,
input CLR,
input CE,
input CE2,
output reg [3:0] Q,
output reg [3:0] Q2,
output wire CEO,
output CEO2
);
wire CLK;
wire CLR;
wire CENABLE;
wire CE2;
wire Q;
wire Q2;
wire CEO;
wire CEO2;
licznik licznik(.CLK(CLK),.CLR(CLR),.CE(CE),.CEO(CENABLE),.Q(Q));
licznik2 licznik2(.CLK(CLK),.CLR(CLR),.CE2(CENABLE),.Q2(Q2),.CEO2(CEO2));
endmodule
TESTBENCH:
`timescale 1ns / 1ps
module testbench;
reg CLK;
reg CLR;
reg CE;
reg CE2;
wire [3:0] Q;
wire [3:0] Q2;
wire CEO;
wire CEO2;
top UUT (
.CLK(CLK),
.CLR(CLR),
.CE(CE),
.CE2(CE2),
.Q(Q),
.Q2(Q2),
.CEO(CEO),
.CEO2(CEO2)
);
initial CLK=1'b0;
always #5 CLK=~CLK;
initial
begin
CLR = 1'b1;
CE= 1'b1;
#18 CLR = 1'b0;
end
endmodule
FIRST MODULE:
`timescale 1ns / 1ps
module licznik(
input CLK,
input CLR,
input CE,
output reg [3:0] Q,
output CEO
);
always #(posedge CLK or posedge CLR)
if(CLR)
Q <= 4'd0;
else begin
if(CE) begin
if(Q != 4'd9)
Q <= Q + 1;
else
Q <= 4'd0;
end
end
assign CEO = CE & (Q == 4'd9);
endmodule
SECOND MODULE:
`timescale 1ns / 1ps
module licznik2(
input CLK,
input CLR,
input CE2,
output reg [3:0] Q2,
output CEO2
);
always #(posedge CLK or posedge CLR)
if(CLR)
Q2 <= 4'd0;
else begin
if(CE2) begin
if(Q2 != 4'd9)
Q2 <= Q2 + 1;
else
Q2 <= 4'd0;
end
end
assign CEO2 = CE2 & (Q2 == 4'd9);
endmodule
I ran your code on 2 simulators, and I got compile errors on both. Try your code on EDAPlayground.
To fix the compile errors, I removed the wire declarations in module top. To fix the problem with Z on CEO, I replaced CENABLE with CEO. Here is the new top module:
module top(
input CLK,
input CLR,
input CE,
input CE2,
output reg [3:0] Q,
output reg [3:0] Q2,
output wire CEO,
output CEO2
);
licznik licznik(.CLK(CLK),.CLR(CLR),.CE(CE),.CEO(CEO),.Q(Q));
licznik2 licznik2(.CLK(CLK),.CLR(CLR),.CE2(CEO),.Q2(Q2),.CEO2(CEO2));
endmodule
CE2 is X because it is an undriven input. I think you can just delete it.
I have written the testbench code and design code for Master-slave JK flip flop, but output isn't coming.
Please point out the error.
Test bench.sv
module JK_ff_tb;
reg clk;
reg reset;
reg j,k;
wire q;
wire qb;
jk_flip_flop_master_slave jkflipflop( .clk(clk), .reset(reset), .j(j), .k(k), .q(q), .q_bar(qb) );
initial begin
$dumpfile("dump.vcd"); $dumpvars;
$monitor(clk,j,k,q,qb,reset);
j = 1'b0;
k = 1'b0;
reset = 1;
clk=1;
#10
reset=0;
j=1'b1;
k=1'b0;
#100
reset=0;
j=1'b0;
k=1'b1;
#100
reset=0;
j=1'b1;
k=1'b1;
#100
reset=0;
j=1'b0;
k=1'b0;
#100
reset=1;
j=1'b1;
k=1'b0;
end
always #25 clk <= ~clk;
endmodule
Design.sv
module jk_flip_flop_master_slave(j,k,clk,reset,q,q_bar);
input j,k,clk,reset;
output q,q_bar;
reg q,q_bar; // Active low reset signal.
wire MQ; // The master's Q output.
wire MQn; // The master's Qn output.
wire Cn; // The clock input to the slave shall be the complement of the master's.
wire J1;
wire K1;
wire J2; // The actual input to the first SR latch (S).
wire K2; // The actual input to the first SR latch (R).
assign J2 = !reset ? 0 : J1; // Upon reset force J2 = 0
assign K2 = !reset ? 1 : K1; // Upon reset force K2 = 1
and(J1, j, q_bar);
and(K1, k, q);
not(Cn, clk);
sr_latch_gated master(MQ, MQn, clk, J2, K2);
sr_latch_gated slave(q, q_bar, Cn, MQ, MQn);
endmodule // jk_flip_flop_master_slave
Sr_Latched flip flop module
module sr_latch_gated(Q, Qn, G, S, R);
output Q;
output Qn;
input G;
input S;
input R;
wire S1;
wire R1;
and(S1, G, S);
and(R1, G, R);
nor(Qn, S1, Q);
nor(Q, R1, Qn);
endmodule // sr_latch_gated
I have coded the entire thing in EDA-playground.
The diagram generated was really abrupt as well.
If there is another logic that can be implemented easily, do tell.
I get compile errors on 2 different simulators. You should not declare q and q_bar as reg in the jk_flip_flop_master_slave module. You should delete this line:
reg q,q_bar; // Active low reset signal.
Then it compiles and simulates for me. I see this output:
100xx1
110xx0
010010
110010
010010
110010
101010
001010
101010
001010
...
I wrote this Verilog code. The inner module is an 8-bit mux, and the top module is used to test the mux. It should display 11110000, but it displayed xxxxxxxx every time. How do I fix this?
module testbench;
reg CLK;
test mytest(CLK);
initial begin
CLK = 1'b0;
#10
CLK = 1'b1;
end
endmodule
module test(CLK);
input CLK;
reg [7:0] in0,in1;
reg sel;
wire [7:0] out;
mux myux(in0,in1,sel,out);
always #(posedge CLK) begin
sel = 1'b0;
in0 = 8'b11110000;
$display("%b",out);
end
endmodule
This is the mux module:
module mux(in0,in1,sel,out);
input sel;
input [7:0] in1,in0;
output [7:0] out;
reg out;
always #(in0,in1,sel) begin
if(sel == 1'b0) begin
out = in0;
end
else begin
out = in1;
end
end
endmodule
The problem is that you did not run your simulation long enough. You only ran it for one clock cycle. Here is one way to change your testbench module to run many clock cycles:
module testbench;
reg CLK;
test mytest(CLK);
initial begin
CLK = 1'b0;
forever #10 CLK =~CLK;
end
initial #1000 $finish;
endmodule
I now see output like this:
xxxxxxxx
11110000
11110000
11110000
11110000
Also, I got a compile error with your code. In your mux module, you should change:
reg out;
to:
reg [7:0] out;
I'm trying to design a 4-bit counter with T-flipflop, here's what i did:
1- From a D-flipflop to T-flipflop:
module T_FlipFlop( clk,T, Q);
input wire clk;
input wire T;
output reg Q;
wire D;
initial
begin
Q<=1'b0;
end
assign D= T ^ Q;
always #(negedge clk)
begin
Q<=D;
end
endmodule
with RTL shematic :
following this "D_ff to T_ff" conversion:
2- Then, i instantiated 4 T-flipflops in the top module and connected the output of each flipflop to the clk of the next one:
module Counters_FreqDividers( sysclk,Q1,Q2,Q3,Q4);
input sysclk;
output wire Q1;
output wire Q2;
output wire Q3;
output wire Q4;
T_FlipFlop num_1(.clk(sysclk),.T(1'b1),.Q(Q1));
T_FlipFlop num_2(.clk(Q1),.T(1'b1),.Q(Q2));
T_FlipFlop num_3(.clk(Q2),.T(1'b1),.Q(Q3));
T_FlipFlop num_4(.clk(Q3),.T(1'b1),.Q(Q4));
endmodule
with RTL schematic :
to follow this diagram:
We know that T-flipflop is just a JK-flipflop with J and K connected to each other and that's what we have here, so consider them as T-flipflops.
3-The simulation:
4- Finally, my questions:
1) why Q1 is the ONLY output that operates properly?
2) Why Q2, Q3, Q4 starts with 1 although i have initialized them as 0?
I can't figure out what's missing, i tried to play around but nothing worked and i'm stuck here!
Edit: my testbench:
module test;
// Inputs
reg sysclk;
// Outputs
wire Q1;
wire Q2;
wire Q3;
wire Q4;
// Instantiate the Unit Under Test (UUT)
Counters_FreqDividers uut (
.sysclk(sysclk),
.Q1(Q1),
.Q2(Q2),
.Q3(Q3),
.Q4(Q4)
);
initial begin
// Initialize Inputs
sysclk <= 1'b1;
#200 $finish();
end
always #5 sysclk=~sysclk;
endmodule
I cannot get a T-Flipflop from a D flipflop to work in Modelsim even after it came directly from class notes. It must be something simple I'm just overlooking.
module D_FF (q, Clk, reset_n,d);
output q;
input Clk, reset_n, d;
reg q;
always #(posedge reset_n or negedge Clk)
if (~reset_n)
q <= 1'b0;
else
q <= d;
endmodule
module T_ff (q, Clk, reset_n);
output q;
input Clk, reset_n;
wire d;
D_FF DFF0 (q, Clk, reset_n, Vcc);
not n1 (d,q);
endmodule
Hi there are two problems:
1. Your reset is active low, so it should be sensitive to the falling edge of the clock.
2. What is that VCC? you should use d there.
Here is the correct version
D_FF:
module D_FF (q, Clk, reset_n,d);
output q;
input Clk, reset_n, d;
reg q;
always #(negedge reset_n or posedge Clk)
if (~reset_n)
q <= 1'b0;
else
q <= d;
endmodule
T_FF:
module T_FF (q, Clk, reset_n);
output q;
input Clk, reset_n;
wire d;
D_FF DFF0 (q, Clk, reset_n, d);
not n1 (d,q);
endmodule