I cannot get a T-Flipflop from a D flipflop to work in Modelsim even after it came directly from class notes. It must be something simple I'm just overlooking.
module D_FF (q, Clk, reset_n,d);
output q;
input Clk, reset_n, d;
reg q;
always #(posedge reset_n or negedge Clk)
if (~reset_n)
q <= 1'b0;
else
q <= d;
endmodule
module T_ff (q, Clk, reset_n);
output q;
input Clk, reset_n;
wire d;
D_FF DFF0 (q, Clk, reset_n, Vcc);
not n1 (d,q);
endmodule
Hi there are two problems:
1. Your reset is active low, so it should be sensitive to the falling edge of the clock.
2. What is that VCC? you should use d there.
Here is the correct version
D_FF:
module D_FF (q, Clk, reset_n,d);
output q;
input Clk, reset_n, d;
reg q;
always #(negedge reset_n or posedge Clk)
if (~reset_n)
q <= 1'b0;
else
q <= d;
endmodule
T_FF:
module T_FF (q, Clk, reset_n);
output q;
input Clk, reset_n;
wire d;
D_FF DFF0 (q, Clk, reset_n, d);
not n1 (d,q);
endmodule
Related
I've been designing a one-shot as part of my EE senior project and am unable to get the 'Reset' to toggle the output to 0.
I used the RTL_viewer in Quartus and the design does match my code: The DFF output (Q) is fed into 2 inverters then into the DFF Reset.
My understanding is that the two inverters should act as buffers. The DFF output should be 0 until the next clock edge is reached. I'm not sure if something is wrong with my design or if this is a timing error. I tried playing around with the clock speed and the buffer delay, but neither produced the correct results.
module oneShot(Clk, Q, Q_bar);
input Clk;
output Q, Q_bar;
logic X, Reset /* synthesis keep */;
logic D = 1'b1;
parameter propogation_delay = 30ns;
not #(propogation_delay) (X, Q);
not #(propogation_delay) (Reset, X);
//instantiation of flip flop
//DFF (Clk, Reset, D, Q);
DFF1 unit0 (Clk, Reset, D, Q);
assign Q_bar = ~ Q;
endmodule
module DFF1 (Clk, Reset, D, Q);
input Clk, Reset, D;
output logic Q;
always_ff #(posedge Clk)
begin
if(Reset == 1'b1)
Q <= 0;
else
Q <= D;
end
endmodule
module oneShot_tb;
logic Clk, Q, Q_bar, Reset;
oneShot DUT (Clk, Q, Q_bar);
always begin
Clk = 0;
#10;
Clk = 1'b1;
#10;
end
initial begin
#300;
$stop;
end
I realize that this may be very easy to fix but I can't find a way to make it work.
My question is how can I get visual signals of CE2 and CEO in this case? I know by looking on RTL Scheme CE2 and CEO isn't connected to pins. And I just can't connect them.
CE2 should be ON when first counter reach 9 but on waveform its always as X. And CEO should be ON when Q is 9 but on waveform its always Z.
This circuit is just for self learning.
Testbench
Circuit Scheme
TOP MODULE:
`timescale 1ns / 1ps
module top(
input CLK,
input CLR,
input CE,
input CE2,
output reg [3:0] Q,
output reg [3:0] Q2,
output wire CEO,
output CEO2
);
wire CLK;
wire CLR;
wire CENABLE;
wire CE2;
wire Q;
wire Q2;
wire CEO;
wire CEO2;
licznik licznik(.CLK(CLK),.CLR(CLR),.CE(CE),.CEO(CENABLE),.Q(Q));
licznik2 licznik2(.CLK(CLK),.CLR(CLR),.CE2(CENABLE),.Q2(Q2),.CEO2(CEO2));
endmodule
TESTBENCH:
`timescale 1ns / 1ps
module testbench;
reg CLK;
reg CLR;
reg CE;
reg CE2;
wire [3:0] Q;
wire [3:0] Q2;
wire CEO;
wire CEO2;
top UUT (
.CLK(CLK),
.CLR(CLR),
.CE(CE),
.CE2(CE2),
.Q(Q),
.Q2(Q2),
.CEO(CEO),
.CEO2(CEO2)
);
initial CLK=1'b0;
always #5 CLK=~CLK;
initial
begin
CLR = 1'b1;
CE= 1'b1;
#18 CLR = 1'b0;
end
endmodule
FIRST MODULE:
`timescale 1ns / 1ps
module licznik(
input CLK,
input CLR,
input CE,
output reg [3:0] Q,
output CEO
);
always #(posedge CLK or posedge CLR)
if(CLR)
Q <= 4'd0;
else begin
if(CE) begin
if(Q != 4'd9)
Q <= Q + 1;
else
Q <= 4'd0;
end
end
assign CEO = CE & (Q == 4'd9);
endmodule
SECOND MODULE:
`timescale 1ns / 1ps
module licznik2(
input CLK,
input CLR,
input CE2,
output reg [3:0] Q2,
output CEO2
);
always #(posedge CLK or posedge CLR)
if(CLR)
Q2 <= 4'd0;
else begin
if(CE2) begin
if(Q2 != 4'd9)
Q2 <= Q2 + 1;
else
Q2 <= 4'd0;
end
end
assign CEO2 = CE2 & (Q2 == 4'd9);
endmodule
I ran your code on 2 simulators, and I got compile errors on both. Try your code on EDAPlayground.
To fix the compile errors, I removed the wire declarations in module top. To fix the problem with Z on CEO, I replaced CENABLE with CEO. Here is the new top module:
module top(
input CLK,
input CLR,
input CE,
input CE2,
output reg [3:0] Q,
output reg [3:0] Q2,
output wire CEO,
output CEO2
);
licznik licznik(.CLK(CLK),.CLR(CLR),.CE(CE),.CEO(CEO),.Q(Q));
licznik2 licznik2(.CLK(CLK),.CLR(CLR),.CE2(CEO),.Q2(Q2),.CEO2(CEO2));
endmodule
CE2 is X because it is an undriven input. I think you can just delete it.
I am building a shift-unit that is capable of arithmetic and logical right shift, and logical left shift depending on the control signals given to it. However, the arithmetic right shift operator output generates output similar to that logical right shift operator, i.e. sign extension does not occur.
Main code
`timescale 1ns / 1ps
module shift_unit(
input [15:0] a,
input [3:0] b,
input clk,
input isLSL,
input isLSR,
input isASR,
output reg [15:0] result
);
wire [15:0] LSL_result, LSR_result, ASR_result;
LSL lsl(a, b, clk, isLSL, LSL_result);
LSR lsr(a, b, clk, isLSR, LSR_result);
ASR asr(a, b, clk, isASR, ASR_result);
always#(posedge clk) begin
case({isLSL, isLSR, isASR})
3'b001: result <= ASR_result;
3'b010: result <= LSR_result;
3'b100: result <= LSL_result;
endcase
end
endmodule
LSL code:
`timescale 1ns / 1ps
module LSL(
input [15:0] a,
input [3:0] b,
input clk,
input isLSL,
output [15:0] out
);
reg [15:0] result;
always#(posedge clk) begin
if(isLSL) result = a << b;
end
assign out = result;
endmodule
LSR code:
`timescale 1ns / 1ps
module LSR(
input [15:0] a,
input [3:0] b,
input clk,
input isLSR,
output [15:0] out
);
reg [15:0] result;
always#(posedge clk) begin
if(isLSR) result = a >> b;
end
assign out = result;
endmodule
ASR code:
`timescale 1ns / 1ps
module ASR(
input [15:0] a,
input [3:0] b,
input clk,
input isASR,
output [15:0] out
);
reg [15:0] result;
always#(posedge clk) begin
if(isASR) result = a >>> b;
end
assign out = result;
endmodule
And finally, the testbench:
`timescale 1ns / 1ps
module shift_unit_test;
reg [15:0] a;
reg [3:0] b;
reg clk;
reg isLSL;
reg isLSR;
reg isASR;
wire [15:0] result;
shift_unit uut (
.a(a),
.b(b),
.clk(clk),
.isLSL(isLSL),
.isLSR(isLSR),
.isASR(isASR),
.result(result)
);
always #5 clk = ~clk;
initial begin
clk = 1'b0;
a = 16'b1100101011001010;
b = 4;
{isLSL, isLSR, isASR} = 3'b100; #100;
{isLSL, isLSR, isASR} = 3'b010; #100;
{isLSL, isLSR, isASR} = 3'b001; #100;
end
endmodule
The above code has been modelled using Xilinx ISE 14.7.
Any help would be greatly appreciated.
You need to be working with signed signals to get sign extension.
module ASR(
input wire signed [15:0] a,
input [3:0] b,
input clk,
input isASR,
output reg signed [15:0] out
);
always#(posedge clk) begin
if(isASR) out = a >>> b;
end
endmodule
I am a beginner in designing circuit using verilog in modelsim. I use a sample code and a tutorial to learn how modelsim works. The code and the testbench are compiled without any problem and even testbench is simulated without any error but the input and output signals are not shown in object windows and they are not under instance menu. please describe for me how can I find them and simulate the waveforms.
here is my code and the test bench.
the definition of a D flipflop
// module D_FF with synchronous reset
module D_FF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
// Lots of new constructs. Ignore the functionality of the
// constructs.
// Concentrate on how the design block is built in a top-down fashion.
always #(negedge clk or posedge reset)
if (reset)
q <= 1'b0;
else
q <= d;
endmodule
the definition of a T flipflop from D
module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q);
endmodule
counter codes:
module rcc4(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module T_FF are created.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule
testbench code:
module stimulus();
reg clk;
reg reset;
wire[3:0] q;
// instantiate the design block
rcc4 r1(q, clk, reset);
// Control the clk signal that drives the design block. Cycle time = 10
initial
clk = 1'b0; //set clk to 0
always
#5 clk = ~clk; //toggle clk every 5 time units
// Control the reset signal that drives the design block
// reset is asserted from 0 to 20 and from 200 to 220.
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish; //terminate the simulation
end
// Monitor the outputs
initial
$monitor($time, " Output q = %d", q);
endmodule
I am using modelsim 10.1c on Windows 10.
The following picture is from my project and it shows my object and instance window.
The switch -voptargs=+acc will solve your issue.
vsim -voptargs=+acc modulename
This my Verilog code to convert the number x into form x=a0*R+a1 ,e.g 51 = 5*10 +1. My code does not work, it cannot enter the always loop.
`timescale 1ns / 1ps
module poly(
input [15:0] r,
input [15:0] x,
output reg[15:0] a1,
output reg [15:0] a0,
output finish,
input clk,
input reset
);
reg [15:0] sum;
assign finish =(sum > x);
always# (posedge clk )
begin
if(reset)
begin
a0 <=0;
sum <=0;
end
else if (!finish)
begin
a0 <=a0+1;
sum <= sum+r;
end
else
a1<=x-sum;
end
initial begin
$monitor ( "a1=%b,a0=%b,finish=%b,reset=%b",a1,a0,finish,reset);
end
endmodule
testbench
`timescale 1ns / 1ps
module tb_p;
reg [15:0] r;
reg [15:0] x;
wire[15:0] a1;
wire [15:0] a0;
wire finish;
reg clk;
reg reset;
initial clk=0;
always #5 clk=!clk;
poly m1(r,x,a1,a0,finish,clk,reset);
initial begin
r<=10;
x <=17;
#1 reset<=1;
#2 reset<=0;
end
endmodule
Since your reset signal is synchronous to the clock, you need to extend it so that it is high for at least one posedge of the clock:
initial begin
r<=10;
x <=17;
#1 reset<=1;
#20 reset<=0;
#500 $finish;
end
Note that I added $finish just so my simulation would end.