convert integer sqrt algorithm to fixed point in verilog - verilog

Question

I've got this code which determines and integer square root of a 32 bit number.
output = floor(sqrt(input))
I want to get a fixed point result such as this {8 bit integer ,8 bit fractionary} but on an 8 bit input. So wire[7:0] input instead of [31:0].
My issue is that I don't know how to modify the algorithm to determine what I previously stated. Below you will find the code.
module sqrt32(clk, rdy, reset, x, .y(acc));
input clk;
output rdy;
input reset;
input [31:0] x;
output [15:0] acc;
// acc holds the accumulated result, and acc2 is the accumulated
// square of the accumulated result.
reg [15:0] acc;
reg [31:0] acc2;
// Keep track of which bit I'm working on.
reg [4:0] bitl;
wire [15:0] bit = 1 << bitl;
wire [31:0] bit2 = 1 << (bitl << 1);
// The output is ready when the bitl counter underflows.
wire rdy = bitl[4];
// guess holds the potential next values for acc, and guess2 holds
// the square of that guess. The guess2 calculation is a little bit
// subtle. The idea is that:
//
// guess2 = (acc + bit) * (acc + bit)
// = (acc * acc) + 2*acc*bit + bit*bit
// = acc2 + 2*acc*bit + bit2
// = acc2 + 2 * (acc<<bitl) + bit
//
// This works out using shifts because bit and bit2 are known to
// have only a single bit in them.
wire [15:0] guess = acc | bit;
wire [31:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
task clear;
begin
acc = 0;
acc2 = 0;
bitl = 15;
end
endtask
initial clear;
always #(reset or posedge clk)
if (reset)
clear;
else begin
if (guess2 <= x) begin
acc <= guess;
acc2 <= guess2;
end
bitl <= bitl - 1;
end
endmodule
module main;
reg clk, reset;
reg [31:0] value;
wire [15:0] result;
wire rdy;
sqrt32 root(.clk(clk), .rdy(rdy), .reset(reset), .x(value), .y(result));
always #5 clk = ~clk;
always #(posedge rdy) begin
$display("sqrt(%d) --> %d", value, result);
$finish;
end
initial begin
clk = 0;
reset = 1;
$monitor($time,,"%m.acc = %b", root.acc);
#100 value = 63;
reset = 0;
end
endmodule /* main */
Improved version:
I've managed to get the algorithm to partially work, following Matt's advice.
There is still this issue:
for input = 70 the result should be output = 8.366
I get
for input = 70 the result is output = 8.5
Is it possible to get the right fractionary part?
I am not getting the right fractionary part and I don't know why or if it is possible: here is the improved algorithm:
module sqrt32(clk, rdy, reset, x, .y(acc));
input clk;
output rdy;
input reset;
input [7:0] x;
output [15:0] acc;
reg [15:0] xholder;
// acc holds the accumulated result, and acc2 is the accumulated
// square of the accumulated result.
reg [15:0] acc;
reg [15:0] acc2;
// Keep track of which bit I'm working on.
reg [4:0] bitl;
wire [15:0] bit = 1 << bitl;
wire [15:0] bit2 = 1 << (bitl << 1);
// The output is ready when the bitl counter underflows.
wire rdy = bitl[4];
// guess holds the potential next values for acc, and guess2 holds
// the square of that guess. The guess2 calculation is a little bit
// subtle. The idea is that:
//
// guess2 = (acc + bit) * (acc + bit)
// = (acc * acc) + 2*acc*bit + bit*bit
// = acc2 + 2*acc*bit + bit2
// = acc2 + 2 * (acc<<bitl) + bit
//
// This works out using shifts because bit and bit2 are known to
// have only a single bit in them.
wire [15:0] guess = acc | bit;
wire [15:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
task clear;
begin
acc = 0;
acc2 = 0;
//bitl = 15;
bitl = 7;
assign xholder = x << 8;
end
endtask
initial clear;
always #(reset or posedge clk)
if (reset)
clear;
else begin
$display("xholder is %b", xholder);
if (guess2 <= xholder) begin
acc <= guess;
acc2 <= guess2;
end
bitl <= bitl - 1;
end
endmodule
module sqrtest;
reg clk, reset;
reg [7:0] value;
wire [15:0] result;
wire rdy;
sqrt32 root(.clk(clk), .rdy(rdy), .reset(reset), .x(value), .y(result));
always #5 clk = ~clk;
always #(posedge rdy) begin
$display("sqrt(%d) --> %d,%d", value, result[7:4], result[3:0]);
$finish;
end
initial begin
clk = 0;
reset = 1;
$monitor($time,"%m.acc = %b", root.acc);
#100 value = 70;
reset = 0;
end
endmodule /* main */

Answer 1

Just ran the simulation of the code with some values and came up with a simple solution.
Note: The code give in the question may not compile successfully as bit is a Verilog reserved word. Also, wire instantiations with assignments on the same line (such as wire [31:0] bit2 = 1 << (bitl << 1);) should really be split up into 2 separate lines (wire [15:0] bit2; assign bit2 = 1 << (bitl << 1);).
Anyways, your input that has 8 bits to represent the integer part and 8 bits to represent the fractional part is really the same as a 16 bit number, the only difference being that it is multiplied by 2^8. So, one possible solution would be to feed your '16' bit integer into the input of the sqrt32 module.
By doing this, you are really solving sqrt(X * 2^8). The output of the function would be sqrt(X) * 2^4. The answer would be the 8 LSBs of the output, where [7:4] is the integer part and [3:0] is the fractional part.