My project is to design a verilog code that gives an output on the 7segments (HEX0,HEX1,HEX2,HEX3) and output must increase when the button KEY0 is pressed on the board 1 by 1, and decrease when the button KEY1 is pressed using Altera Board (Cyclone II-EP2C35F672).
I achieve to increase 1 by 1 but when I try to decrease with the same logic, I take irrelevant outputs. Is it possible to give me a way solving the problem.
My verilog code is that:
module sevensegment (KEY,HEX0,HEX1,HEX2,HEX3);
input [3:0]KEY;
output [0:6]HEX0;
output [0:6]HEX1;
output [0:6]HEX2;
output [0:6]HEX3;
counter D1(~KEY,HEX0,HEX1,HEX2,HEX3);
endmodule
module counter(in,out,out1,out2,out3);
input [3:0]in;
output [6:0]out;
output [6:0]out1;
output [6:0]out2;
output [6:0]out3;
reg[15:0] tmp;
always #(posedge in)
begin
if(~in[0])
begin
tmp <= tmp + 1'b1;
end
else if(~in[1])
begin
tmp <= tmp - 1'b1;
end
end
displaysevensegment first_digit(tmp[3:0],out);
displaysevensegment second_digit(tmp[7:4],out1);
displaysevensegment third_digit(tmp[11:8],out2);
displaysevensegment fourth_digit(tmp[15:12],out3);
endmodule
module displaysevensegment(in,out);
// abcdefg
parameter BLANK = 7'b1111111;
parameter ZERO = 7'b0000001;
parameter ONE = 7'b1001111;
parameter TWO = 7'b0010010;
parameter THREE = 7'b0000110;
parameter FOUR = 7'b1001100;
parameter FIVE = 7'b0100100;
parameter SIX = 7'b0100000;
parameter SEVEN = 7'b0001111;
parameter EIGHT = 7'b0000000;
parameter NINE = 7'b0000100;
parameter TEN = 7'b0001000;
parameter ELEVEN = 7'b1100000;
parameter TWELVE = 7'b0110001;
parameter THIRTEEN = 7'b1000010;
parameter FOURTEEN = 7'b0110000;
parameter FIFTEEN = 7'b0111000;
input [3:0]in;
output [6:0]out;
assign out = (in == 0) ? ZERO:
(in == 1) ? ONE:
(in == 2) ? TWO:
(in == 3) ? THREE:
(in == 4) ? FOUR:
(in == 5) ? FIVE:
(in == 6) ? SIX:
(in == 7) ? SEVEN:
(in == 8) ? EIGHT:
(in == 9) ? NINE:
(in == 10) ? TEN:
(in == 11) ? ELEVEN:
(in == 12) ? TWELVE:
(in == 13) ? THIRTEEN:
(in == 14) ? FOURTEEN:
(in == 15) ? FIFTEEN:BLANK;
endmodule
The simulate will not recognize the raising edge of in[1] when the sensitivity list is describes as posedge in. Only the LSB will be monitored. Instead use a bitwise operation to detect when a key is pressed and use this as the clocking signal.
wire gen_clk = |in; // bitwise OR
always #(posedge gen_clk) begin
if (in[0]) tmp <= tmp + 1'b1;
else if (in[1) tmp <= tmp - 1'b1;
end
wire gen_clk = ∈ // bitwise AND
always #(posedge gen_clk) begin
if (in[0]) tmp <= tmp + 1'b1;
else if (in[1) tmp <= tmp - 1'b1;
end
Side note: Deep nested muxes often result in lower performance more area then a case statement. This is because most synthesizer will not optimize inline muxes (?:). Recommend re-coding displaysevensegment with a case statement like:
input [3:0] in;
output [6:0] out;
reg [6:0] out; // out needs to be a reg
always #* begin
case(in)
4'h0 : out = ZERO;
4'h1 : out = ONE;
// ...
4'hE : out = FOURTEEN;
4'hF : out = FIFTEEN;
default: out = BLANK;
endcase
end
Related
What I'm designing is a moore machine that gives particular color for each state.
Here's a part of my code.
always #(*) begin
case (state)
S0 : led = 6'b111111;
S1 : led = 6'b010100; // have to blink //
S2 : led = 6'b100010;
S3 : led = 6'b110110;
default : led_output = 6'b000000;
endcase
end
endmodule
Before the code shown above, there are codes about assigning state corresponding to the input.
The code shown above is to determine the output value of moore machine. (Therefore the condition is *)
What I left is to assign led output value for each state.
However the condition for S1 is not only particular color but it has to 'blink' for period of 1s.
I already googled for 'blink LED' verilog code but they were little bit different from my situation.
I have no idea of coding block that is needed.
Can you give me some advice or answer for what to add to make S1 to blink?
To make it blink, you need to distinguish 2 states. So create a 1-bit signal, say sel, which toggles in S1 state, and its toggle speed as well as its duty meet your requirement in 'blink' for period of 1s. This is basically implemented with the help of a counter.
reg [3:0] cnt; // assume 4-bit long
reg sel;
// counter to determine the HIGH / LOW time of sel.
always#(posedge clk or negedge resetn)begin
if(!resetn)begin
cnt <= 4'h0;
end
// since you can exit S1 state at any time using push_button,
// make sure cnt is always ZERO when entering S1 state next time.
// also to save power when using clock gating, because this statement
// is only active for 1 cycle.
else if((state == S1) & ((push_button == 2'b01) | (push_button == 2'b10)))begin // S1 exit condition
cnt <= 4'h0;
end
else if(state == S1)begin
// sel HIGH lasts <HIGH_MAX_VAL>+1 cycles
// sel LOW lasts <LOW_MAX_VAL>+1 cycles
if(cnt == (sel ? <HIGH_MAX_VAL> : <LOW_MAX_VAL>))begin
cnt <= 4'h0;
end
else begin
cnt <= cnt + 4'h1;
end
end
end
always#(posedge clk or negedge resetn)begin
if(!resetn)begin
sel <= 1'h0;
end
else if((state == S1) & ((push_button == 2'b01) | (push_button == 2'b10)))begin
sel <= 1'h0;
end
else if(state == S1)begin
if(cnt == (sel ? <HIGH_MAX_VAL> : <LOW_MAX_VAL>))begin
sel <= ~sel;
end
end
end
Use sel to select between 2 led values.
always#(*)begin
case(state)
....
S1 : led = sel ? 6'b010100 : <ANOTHER_VALUE>;
....
endcase
end
I want to write a Serial to Parallel conversion in Verilog, and I can't realize what is wrong with my code. It doesn't synthesize, and not even the ISE shows what the problem is. Can anyone help me?
I guess the problem is around the second always block. The part:
if (STATE == TRANSMIT)
PAR_OUT[COUNTER] = SER_IN;
seems wrong to me, but I can't understand what to change or test.
module SIPO(
input SER_IN,
input RST,
input CLK,
input LOAD,
output reg READY,
output reg [7:0] PAR_OUT
);
parameter IDLE = 2'b00, START = 2'b01, TRANSMIT = 2'b10, STOP = 2'b11;
reg [1:0] STATE;
reg [2:0] COUNTER;
always # ( posedge CLK or negedge RST)
if (~RST)
begin
STATE <= IDLE;
READY <= 1;
COUNTER <= 0;
end
else
begin
if (STATE == IDLE)
begin
READY <= 1;
COUNTER <= 0;
if (LOAD)
begin
STATE <= START;
end
else
STATE <= IDLE;
end
else
if (STATE == START)
STATE <= TRANSMIT;
else
if (STATE == TRANSMIT)
begin
COUNTER <= COUNTER + 1;
if (COUNTER == 7)
STATE <= STOP;
end
else
begin
STATE <= IDLE;
READY <= 1;
end
end
always #( * )
begin
if (STATE == IDLE)
PAR_OUT = 1;
else
if (STATE == START)
PAR_OUT = 0;
else
if (STATE == TRANSMIT)
PAR_OUT[COUNTER] = SER_IN;
else
PAR_OUT = 1;
end
endmodule
I think your suspicion might be correct regarding PAR_OUT[COUNTER]. When I synthesize your code on edaplayground with Yosys, it infers latches for PAR_OUT, which you likely do not want.
PAR_OUT is 8 bits wide, but you only assign 1 of the 8 bits at a time in the TRANSMIT state, which means the other 7 bits retain their state. For example, if COUNTER=3, then only PAR_OUT[3] is assigned.
I recoded your combo logic, simplifying it with a case statement to make the issue more evident (it should be functionally equivalent to your if/else code):
always #* begin
case (STATE)
TRANSMIT: PAR_OUT[COUNTER] = SER_IN; // Assign to only 1 bit <---
START : PAR_OUT = 8'h00; // Assign to all 8 bits
default : PAR_OUT = 8'h01; // Assign to all 8 bits
endcase
end
If you can afford one cycle of latency, you could use sequential logic for PAR_OUT, such as a shift register.
Problem: I'm synthesizing my code, which reads 1200 16 bit binary vectors, analyzes them and sets a 2 bit register named classe depending on the behavior of 4 if statements. The problem seems to be that classe is stuck on the last if statement - where classe is set to bit 11, or 3.
My code worked fine in when I was using a testbench.
I'm thinking it is stuck because somehow the always block is reading all 1200 vectors at once, as seen in the simulation, instead of one every clock edge?
I've attached a simulation screenshot here: https://imgur.com/a/No2E9cq
module final_final_code
(
output reg [ 0:1] classe
);
reg [0:15] memory [0:1199];
reg[0:15] vect:
integer i;
//// Internal Oscillator
defparam OSCH_inst.NOM_FREQ = "2.08";
OSCH OSCH_inst
(
.STDBY(1'b0), // 0=Enabled, 1=Disabled also Disabled with Bandgap=OFF
.OSC(osc_clk),
.SEDSTDBY() // this signal is not required if not using SED
);
initial begin
$readmemb("C:/Users/KP/Desktop/data.txt", memory, 0, 1199);
i = 0;
end
always #(posedge osc_clk) begin
vect = memory[i];
if ((memory[i][3] == 1'b0)) begin
classe = 2'b10;
end
if ((memory[i][11] == 1'b0)) begin
classe = 2'b01;
end
if ((memory[i][8] == 1'b1 && memory[i][4] + memory[i][5] + memory[i][6] + memory[i][7] >= 4'b0100)) begin
classe = 2'b00;
end
if ((memory[i][0] + memory[i][1] + memory[i][2] + memory[i][3] + memory[i][4] + memory[i][5] + memory[i][6] + memory[i][7] + memory[i][8] + memory[i][9] + memory[i][10] + memory[i][11] + memory[i][12] + memory[i][13] + memory[i][14] + memory[i][15] <= 1'b1)) begin
classe = 2'b11;
end
i = i + 1'd1;
if (i == 4'd1199) begin
i = 0;
end
end
endmodule
Apart from what john_log says:
Your last if statement is always TRUE. You are adding 1-bit operands and comparing against a 1-bit result thus the results is 1'b1 or 1'b0 which is always <= 1'b1.
You should check if your FPGA tool supports this:
initial begin
$readmemb("C:/Users/KP/Desktop/data.txt", memory, 0, 1199);
i = 0;
end
Especially the loading of a memory from a file by the synthesis tool. It was not possible the last time I used an FPGA.
I'm new to Verilog. When I try to write code for a finite state machine. I get :
[Synth 8-434] mixed level sensitive and edge triggered event controls are not supported for synthesis
Here is my code:
module controller1(x, clk, s, v);
input x;
input clk;
output s;
output v;
reg [2:0] state;
reg s;
reg v;
always # (negedge clk or x) begin
case (state)
3'b0 : begin
state <= x ? 3'b1 : 3'b10;
s = x ? 0 : 1;
v = 0;
end
3'b10 : begin
state <= x ? 3'b11 : 3'b101;
s = x ? 0 : 1;
v = 0;
end
3'b1 : begin
state <= 3'b11;
s = x ? 1 : 0;
v = 0;
end
3'b101 : begin
state <= 3'b100;
s = x ? 1 : 0;
v = 0;
end
3'b11 : begin
state <= x ? 3'b111 : 3'b100;
s = x ? 0 : 1;
v = 0;
end
3'b100 : begin
state <= 3'b0;
s = x ? 1 : 0;
v = 0;
end
3'b111 : begin
state <= 3'b0;
s = x ? 0 : 1;
v = x ? 1 : 0;
end
endcase
end
endmodule
The question is:
A sequential circuit has
one 1-bit input (X)
a clock input (CLK)
two 1-bit outputs (S and V)
X represents a 4-bit binary number N. The 4-bit number will input one digit a time and start from the least significant bit (LSB).
S represents a 4-bit binary number equal to N + 3. The LSB of S will be output first
when the fourth bit input occurs, V = 1 if N + 3 is too large to be
represented by 4 bits; otherwise, V = 0.
circuit always resets after the fourth bit of X is received. Assume the sequential circuit is implemented with the following
state table.
The outputs are (S,V). All state changes occur on the falling edge of the clock pulse.
If my code has problem to get the required result, please point out. Thanks！
Basically every always block is describing a group of flip-flop, a group of latch, or a block of combinational circuit.
In your code you have mixed edge and level sensitivity by using 'negedge clock' and 'x'. If your FSM is sensitive to only falling edge of clock then remove 'x' from sensitivity list of always block.
Mixed sensitive list of levels and edges is not synthesizable, because a flip-flop cannot be edge-tiggered and level-triggered at the same time.
Check this link:
Synthesis of `always` blocks
In the following code BCDtoSevenDecode takes 4 bit input and decodes it for Seven Segment display. The decoded result is stored in resultx variable. All resultx variables are then passed to a 4x1 Mux. I am using xilinx to compile this verilog code. The code compiles with the warning:
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <select> is never assigned.
I am unable to figure out the problem so I am consulting experts here.
Here is the code:
module Counter(input clk, input reset, output[3:0]SsdEnable, output [6:0]DecodedOut, output reg [3:0]temp1, output reg [3:0]temp2 , output reg [3:0]temp3, output reg [3:0]temp4);
wire [6:0] Result1,Result2,Result3,Result4;
reg [3:0] count1,count2,count3,count4;
wire [25:0]loop;
wire [11:0]counter;
reg [1:0]Sel;
SevenDecoder u1(count1,Result1);
SevenDecoder u2(count2,Result2);
SevenDecoder u3(count3,Result3);
SevenDecoder u4(count4,Result4);
Mux u5(Result1,Result2,Result3,Result4,Sel,DecodedOut );
Decoder_2x4 u6(Sel,SsdEnable);
always #(posedge clk or negedge reset)
begin
if(!reset)
begin
count1<=0;
count2<=0;
count3<=0;
count4<=0;
//counter=0;
end
else
begin
if(loop==49999999)
begin
count1<=count1+1;
if(count1==10)
begin
count1<=0;
count2<=count2+1;
end
if(count2==10)
begin
count2<=0;
count3<=count3+1;
end
if(count3==10)
begin
count3<=0;
count4<=count4+1;
end
if(count4==10)
begin
count1<=0;
count2<=0;
count3<=0;
count4<=0;
end
temp1<=count1;
temp2<=count2;
temp3<=count3;
temp4<=count4;
end
loop=loop+1;
end
end
always #(posedge clk or negedge reset)
begin
if(!reset)
Sel=0;
else
begin
if(counter==1000)
begin
Sel=0;
end
end
counter=counter+1;
end
endmodule
module SevenDecoder(input [3:0]i , output[6:0] out);
assign out[0]= (i == 0 || i == 2 || i == 3 || i == 5 || i == 6 || i == 7 || i == 8 || i == 9) ? 0 : 1;
assign out[1] = (i == 0 || i == 1 || i == 2 || i == 3 || i == 4 || i == 7 || i == 8 || i == 9) ? 0 : 1;
assign out[2] = (i == 0 || i == 1 || i == 3 || i == 4 || i == 5 || i == 6 || i == 7 || i == 8 || i == 9) ? 0 : 1;
assign out[3]= (i == 0 || i == 2 || i == 3 || i == 5 || i == 6 || i == 8 || i == 9) ? 0 : 1;
assign out[4]= (i == 0 || i == 2 || i == 6 || i == 8) ? 0 : 1;
assign out[5]= (i == 0 || i == 4 || i == 5 || i == 6 || i == 8 || i == 9) ? 0 : 1;
assign out[6]= (i == 2 || i == 3 || i == 4 || i == 5 || i == 6 || i == 8 || i == 9) ? 0 : 1;
endmodule
module Mux(input [6:0]in1,input [6:0]in2,input [6:0]in3,input [6:0]in4, input [1:0]sel, output [6:0]out);
assign out=(sel==0)?in1:
(sel==1)?in2:
(sel==2)?in3:
(sel==3)?in4:0;
endmodule
module Decoder_2x4(input [1:0]sel, output [3:0]selSSD);
assign selSSD=(sel==0)? 4'b1110 :
(sel==1)? 4'b1101 :
(sel==2)? 4'b1011 :
(sel==3)? 4'b0111 :0;
endmodule
What is causing this problem?
EDIT:
I have posted the whole code here. I have been trying to debug it but I have failed to find the bug in this code.
This code doesn't give anyoutput. It should display changing values on cnt1,cnt2,cnt3,cnt4 as a proof that values are incrementing but it is not.
Updating answer based on current revison of code in question, some of the further info may no longer apply to the latest version of the question.
The Question contains this block of code:
always #(posedge clk or negedge reset)
begin
if(!reset)
Sel=0;
else
begin
if(counter==1000)
begin
Sel=0;
end
end
counter=counter+1;
end
I would update it to the following :
counter is not reset so will be x, x+1 is till x.
always #(posedge clk or negedge reset) begin
if(!reset) begin
Sel <= 0;
counter <= 0;
end
else begin
counter <= counter+1;
if(counter==1000) begin
Sel <= 0;
end
end
end
endmodule
I noticed this in part of the code, you will not be getting the behaviour you want:
if(iterator==20) begin
if(out[3:0]==9) begin
out[3:0] <= 0;
out[7:4] <= out[7:4]+1;
end
...
out[3:0]<=out[3:0]+1;
The non-blocking assignments mean it does not block the execution of the simulator until the end of the timestep when it copies the value across. So I do not see how out[3:0]<=0 is ever executed as it is unconditionally overridden by out[3:0]<=out[3:0]+1;
The top level module is CounterTOP, with output [7:0] output, this is being driven by the [6:0] output 'out' of MUX. Therefore the MSB (most significant bit) of out will be z, that is undriven.
Some recommended improvements below:
I would avoid mixing the case of variables, you Sel and modules called Mux. I prefer to keep everything lowercase except (local) parameters which are uppercase. Under score delimited is often used over CamelCase. ie I would have written module SevenDecoder as seven_decoder. I think this aids readability and some simulators are not case sensitive so when using mixed case it is possible to have variables differentiated by case which start interfering with each other. Mixing case of variables makes typos more likely.
Bugs are easier to see with correctly aligned code, editing can also be faster as you can start using the column mode of you editor.
Reviewing code is much easier if you use named ports, without it is very hard to spot connectivity errors.
Mux az(
.sel( ),
.in1( result1),
.in2( result2),
.in3( result3),
.in4( result4),
.clk( clk ),
.rst( reset ),
.out( out )
);
Although unrleated to the current error you are seeing I suggest you fix your assignments in always #(posedge clk) blocks.
You are currently using blocking = assignments which can lead to differences between simulation and hardware. which becomes very difficult to debug. in clock triggered block you should use non-blocking <= assignments.
The nested if statements could also be replaced with a case statement:
always #(posedge clk or negedge reset) begin
if(~reset) begin
iterator <=0;
i <=0;
end
else begin
case(iterator)
10, 20, 30 : begin
i <= i+1;
iterator <= iterator + 1;
end
40 : begin
i <= i+1;
iterator <= 0;
end
default : iterator <= iterator+1;
endcase
end
It looks like you haven't connected any select lines to your mux.