Block is unconnected and will be trimmed Verilog - verilog

Question

In the following code BCDtoSevenDecode takes 4 bit input and decodes it for Seven Segment display. The decoded result is stored in resultx variable. All resultx variables are then passed to a 4x1 Mux. I am using xilinx to compile this verilog code. The code compiles with the warning:
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <select> is never assigned.
I am unable to figure out the problem so I am consulting experts here.
Here is the code:
module Counter(input clk, input reset, output[3:0]SsdEnable, output [6:0]DecodedOut, output reg [3:0]temp1, output reg [3:0]temp2 , output reg [3:0]temp3, output reg [3:0]temp4);
wire [6:0] Result1,Result2,Result3,Result4;
reg [3:0] count1,count2,count3,count4;
wire [25:0]loop;
wire [11:0]counter;
reg [1:0]Sel;
SevenDecoder u1(count1,Result1);
SevenDecoder u2(count2,Result2);
SevenDecoder u3(count3,Result3);
SevenDecoder u4(count4,Result4);
Mux u5(Result1,Result2,Result3,Result4,Sel,DecodedOut );
Decoder_2x4 u6(Sel,SsdEnable);
always #(posedge clk or negedge reset)
begin
if(!reset)
begin
count1<=0;
count2<=0;
count3<=0;
count4<=0;
//counter=0;
end
else
begin
if(loop==49999999)
begin
count1<=count1+1;
if(count1==10)
begin
count1<=0;
count2<=count2+1;
end
if(count2==10)
begin
count2<=0;
count3<=count3+1;
end
if(count3==10)
begin
count3<=0;
count4<=count4+1;
end
if(count4==10)
begin
count1<=0;
count2<=0;
count3<=0;
count4<=0;
end
temp1<=count1;
temp2<=count2;
temp3<=count3;
temp4<=count4;
end
loop=loop+1;
end
end
always #(posedge clk or negedge reset)
begin
if(!reset)
Sel=0;
else
begin
if(counter==1000)
begin
Sel=0;
end
end
counter=counter+1;
end
endmodule
module SevenDecoder(input [3:0]i , output[6:0] out);
assign out[0]= (i == 0 || i == 2 || i == 3 || i == 5 || i == 6 || i == 7 || i == 8 || i == 9) ? 0 : 1;
assign out[1] = (i == 0 || i == 1 || i == 2 || i == 3 || i == 4 || i == 7 || i == 8 || i == 9) ? 0 : 1;
assign out[2] = (i == 0 || i == 1 || i == 3 || i == 4 || i == 5 || i == 6 || i == 7 || i == 8 || i == 9) ? 0 : 1;
assign out[3]= (i == 0 || i == 2 || i == 3 || i == 5 || i == 6 || i == 8 || i == 9) ? 0 : 1;
assign out[4]= (i == 0 || i == 2 || i == 6 || i == 8) ? 0 : 1;
assign out[5]= (i == 0 || i == 4 || i == 5 || i == 6 || i == 8 || i == 9) ? 0 : 1;
assign out[6]= (i == 2 || i == 3 || i == 4 || i == 5 || i == 6 || i == 8 || i == 9) ? 0 : 1;
endmodule
module Mux(input [6:0]in1,input [6:0]in2,input [6:0]in3,input [6:0]in4, input [1:0]sel, output [6:0]out);
assign out=(sel==0)?in1:
(sel==1)?in2:
(sel==2)?in3:
(sel==3)?in4:0;
endmodule
module Decoder_2x4(input [1:0]sel, output [3:0]selSSD);
assign selSSD=(sel==0)? 4'b1110 :
(sel==1)? 4'b1101 :
(sel==2)? 4'b1011 :
(sel==3)? 4'b0111 :0;
endmodule
What is causing this problem?
EDIT:
I have posted the whole code here. I have been trying to debug it but I have failed to find the bug in this code.
This code doesn't give anyoutput. It should display changing values on cnt1,cnt2,cnt3,cnt4 as a proof that values are incrementing but it is not.

Answer 1

Updating answer based on current revison of code in question, some of the further info may no longer apply to the latest version of the question.
The Question contains this block of code:
always #(posedge clk or negedge reset)
begin
if(!reset)
Sel=0;
else
begin
if(counter==1000)
begin
Sel=0;
end
end
counter=counter+1;
end
I would update it to the following :
counter is not reset so will be x, x+1 is till x.
always #(posedge clk or negedge reset) begin
if(!reset) begin
Sel <= 0;
counter <= 0;
end
else begin
counter <= counter+1;
if(counter==1000) begin
Sel <= 0;
end
end
end
endmodule
I noticed this in part of the code, you will not be getting the behaviour you want:
if(iterator==20) begin
if(out[3:0]==9) begin
out[3:0] <= 0;
out[7:4] <= out[7:4]+1;
end
...
out[3:0]<=out[3:0]+1;
The non-blocking assignments mean it does not block the execution of the simulator until the end of the timestep when it copies the value across. So I do not see how out[3:0]<=0 is ever executed as it is unconditionally overridden by out[3:0]<=out[3:0]+1;
The top level module is CounterTOP, with output [7:0] output, this is being driven by the [6:0] output 'out' of MUX. Therefore the MSB (most significant bit) of out will be z, that is undriven.
Some recommended improvements below:
I would avoid mixing the case of variables, you Sel and modules called Mux. I prefer to keep everything lowercase except (local) parameters which are uppercase. Under score delimited is often used over CamelCase. ie I would have written module SevenDecoder as seven_decoder. I think this aids readability and some simulators are not case sensitive so when using mixed case it is possible to have variables differentiated by case which start interfering with each other. Mixing case of variables makes typos more likely.
Bugs are easier to see with correctly aligned code, editing can also be faster as you can start using the column mode of you editor.
Reviewing code is much easier if you use named ports, without it is very hard to spot connectivity errors.
Mux az(
.sel( ),
.in1( result1),
.in2( result2),
.in3( result3),
.in4( result4),
.clk( clk ),
.rst( reset ),
.out( out )
);
Although unrleated to the current error you are seeing I suggest you fix your assignments in always #(posedge clk) blocks.
You are currently using blocking = assignments which can lead to differences between simulation and hardware. which becomes very difficult to debug. in clock triggered block you should use non-blocking <= assignments.
The nested if statements could also be replaced with a case statement:
always #(posedge clk or negedge reset) begin
if(~reset) begin
iterator <=0;
i <=0;
end
else begin
case(iterator)
10, 20, 30 : begin
i <= i+1;
iterator <= iterator + 1;
end
40 : begin
i <= i+1;
iterator <= 0;
end
default : iterator <= iterator+1;
endcase
end

Answer 2

It looks like you haven't connected any select lines to your mux.