Implementing CRC32 module with verilog for FPGA - switch-statement

Question

I'm sort of new to FPGA. I'm having a project on this field this summer which is implementing Ethernet switch with 4ports. I've coded all the parts to check preamble and MAC address and etc and they're working correctly
but I have serious problem with implementing CRC32.
I know the algorithm of CRC32 from IEEE 802.3
then, created a frame with 18 Bytes of data
then generated the CRC of my frame with this applet ( here's a link!
but with any frame I make, the result of checking CRC for that particular frame is wrong ( means with my module, every frame has error )
I'd be more than happy to know your opinion
Here is my code of CRC32 module :
module CRC( clk10x, clk, rst, SFD, length, lengthReady, dataIn, hasError//, MACready
);
.
.
// input and outputs and registers are here
.
.
.
initial
begin
CRC <= 32'h04C11DB7;
zeros <= 32'h00000000;
end
always # ( posedge clk10x )
begin
if ( rst )
begin
counter32bit <= 0;
shiftFlag <= 1;
shift <= 0;
shift2 <= 0;
first32bit <= 0;
state <= 0;
index <= 0;
calcEnd <= 0;
end
else if ( clk )
begin
if ( SFD )
begin
case ( state )
'b00 : begin
first32bit <= ( counter32bit == 32 ) ? 1 : 0;
state <= ( first32bit ) ? 'b01 : 'b00;
{MSB, window} <= {window, ~dataIn}; // shift Register;
counter32bit <= counter32bit + 1;
end
'b01 : begin
{MSB, window} <= ( MSB ) ? ( {window, dataIn} ^ CRC ) : {window, dataIn};
shift <= ( lengthReady && shiftFlag ) ? ( length * 8 ) : shift - 1;
shiftFlag <= ( lengthReady ) ? 0 : shiftFlag;
shift2 <= ( shift == 0 && lengthReady ) ? 32 : shift2 -1;
//shift2 <= ( !shift2 ) ? shift2 - 1 : shift2;
state <= ( shift2 == 2 && lengthReady ) ? 'b10 : 'b01;
end
'b10 : begin
{MSB, window} <= ( MSB && !calcEnd ) ? ( {window, zeros[index]} ^ CRC ) : {window, zeros[index]};
index <= ( index == 32 && !calcEnd ) ? 40 : index + 1;
calcEnd <= ( index == 40 ) ? 1 : 0;
state <= ( calcEnd ) ? 'b11 : state;
end
'b11 : begin
window <= window ^ 32'b11111111_11111111_11111111_11111111;
hasError <= ( window == 0 ) ? 0 : 1;
end
default : begin
//state <= 0;
first32bit <= 0;
//shift <= 0;
end
endcase
// have to assign index 0 again
end

Answer 1

CRC calculations are realized on a per bit basis. so every input data word - lets say one byte per clock cycle # 125 MHz for gigabit Ethernet - results in 8 CRC calculations per clock cycle. So your code needs an extra loop to do this 8 sub-cycle calculations.
I would also advice to split up your fsm into a control state machine and crc calculation (data path).
As Mark Adler noticed, the initial value of the CRC's internal LFSR must be initialized with 0xFFFFFFFF. I can see this in your code.
Why do you use 2 different clocks in your process?
Edit 1:
I'm not so good in coding verilog, so I'll copy some VHDL code from our VHDL library. I think you will be able to translate the statements into corresponding verilog code.
I spared the separate register process with reset and clock enable :)
-- Compute next combinational Value
process(lfsr, din)
variable v : std_logic_vector(lfsr'range);
begin
v := lfsr;
for i in BITS-1 downto 0 loop
v := (v(v'left-1 downto 0) & '0') xor
(GN and (GN'range => (din(i) xor v(v'left))));
end loop;
lfsn <= v;
end process;
BITS is a generic and set to 32
lfsr (linear feedback shift register) is 32 bit wide and stores the current "checksum"
the temp. variable v is initialized by the current register value (lfsr)
the for loop goes over every bit of din (data in) and performs the crc calculation (shift + xor)
=> so 32 CRC calculations are performed per clock cycle
GN is the normalized generator polynomial of CRC32
the result is stored in lfsn (next lfsr value) which is connected to a 32 bit wide D-FF with reset and clock enable