I'm checking primality of a number in a form of 6n+1 or 6n-1. I have the below code, but it doesn't seem to be generated correct result.
module prime(clk, rst, start, A, ready, P);
input clk, rst, start;
input [7:0] A;
output ready, P;
reg ready, P;
reg [7:0] divisor;
reg val;
always # (posedge clk or negedge rst) begin
if (!rst) begin
P <= 1'bx;
end
else if (start)
begin
case (A)
-1 : P <= 1;
0 : P <= 1;
1 : P <= 1;
2 : P <= 1;
3 : P <= 1;
5 : P <= 1;
endcase
if (A%2 == 0 && A != 2) begin
P <= 0;
ready <= 1;
end
else if(A > 6)
begin
for(divisor = 5; divisor <= A/divisor; divisor=divisor+6) begin
if (A%divisor == 0 || A%(divisor+2) == 0) begin
P <= 0;
end
end
if (P != 0 && P == 1'bx) begin // need to fix
P <= 1;
end
end
end
end
endmodule
The point is that this part doesn't seem to be working:
if (P != 0 && P == 1'bx)
How can I check whether a variable includes unknown logic, meaning x. Checking as the above
P == 1'bx
doesn't seem to be working.
You should rather use case equality operator (===), which tests 4-state logical equality, then logical equality operator (==).
For the == operator, the result is x, if either operand contains an x or a z.
For the === operator bits with x and z are included in the comparison.
Related
I am getting this error when synthesizing my code, but I don't know what it means. It reads:
Error- net "Count[0] or a directly connected net is driven by more
than one source and not all drivers are three state.
It says the same errors for vectors count[0] - count[4] as well as for my load and k values. The code is my representation of an SPI Master. The SPI master has an instantiation of a shift register that is used to push out information.
module SPIMaster(output reg SCLK, CS, MOSI,
input EN, CLK, MISO,
input [7:0] m_data);
wire master_out;
reg [4:0] count;
wire [7:0] data_buff;
wire SCLK1;
reg master_in, c_sw, k, state, load;
shiftReg register_out (master_out, data_buff, load, (~SCLK), master_in, m_data);
assign SCLK1 = (~c_sw) | CLK;
always#(posedge CLK) begin
if(state) begin
if (k == 1) begin
state <= 0;
c_sw <= 0;
CS <= 1;
count <= 0;
k <= 0;
load <= 0;
end
else begin
state <= 1;
c_sw <= 1;
CS <= 0;
end
end
else begin
if (EN == 1) begin
state <= 1;
c_sw <= 1;
CS <= 0;
count <= 0;
k <= 0;
load <= 1;
end
else begin
state <= 0;
c_sw <= 0;
CS <= 1;
count <= 0;
k <= 0;
load <= 0;
end
end
end
always#(posedge SCLK1) begin
if (CS == 0) master_in <= MISO;
if (count == 7) begin
load <= 0;
end
else if (count == 15)begin
load <= 0;
end
else begin
load <= 1;
end
end
always#(negedge SCLK1) begin
if (count == 23) k <= 1;
else k <= 0;
if (CS == 0) begin
MOSI <= master_out;
count <= count + 1;
end
end
endmodule
Your code does not adhere to good synthesis coding practices because you assign to count from 2 different always blocks and those 2 blocks are triggered by different clock signals. You should make all assignments to count from the same always block.
The same is true of load and k.
I am working on designing a finite state machine in Verilog to represent a stack. The module is as follows:
module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output reg OF_Err = 0, UF_Err = 0;
reg [2:0] y, Y;
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
always #(s, y, Enable)
if (Enable)
begin
case (y)
A: if (s == 3'b000) Y = B;
else
begin
Y = A;
UF_Err = 1;
end
B: if (s == 3'b000) Y = C;
else if (s == 3'b001) Y = A;
else
begin
Y = B;
UF_Err = 1;
end
C: if (s == 3'b000) Y = D;
else if (s == 3'b100) Y = C;
else Y = B;
D: if (s == 3'b000) Y = E;
else if (s == 3'b100) Y = D;
else Y = C;
E: if (s == 3'b000)
begin
Y = E;
OF_Err = 1;
end
else if (s == 3'b100) Y = E;
else Y = D;
default: Y = 3'bxxx;
endcase
c[1] = y[1];
c[0] = y[0];
end
always #(negedge Resetn, posedge Clock)
begin
if (Resetn == 0)
begin
y <= A;
OF_Err = 0; //Problem
UF_Err = 0; //Problem
end
else y <= Y;
end
OF_Err and UF_Err are indicators of overflow and underflow errors, respectively.
However, I get the following errors when compiling my project:
Error (10028): Can't resolve multiple constant drivers for net "OF_Err" at state_machine.v(59)
Error (10029): Constant driver at state_machine.v(10)
Error (10028): Can't resolve multiple constant drivers for net "UF_Err" at state_machine.v(59)
These only appeared after I added the commented lines. I want to reset the over- and underflow indicators when the FSM is reset, but I can't do it the way I have it. How do I go about doing this?
(If it's of any value, this is to be executed on an Altera DE2-115).
In two always blocks you have assigned the values to OF_Err and UF_Err. This is the reason it is showing multiple constant driver error.
module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output OF_Err, UF_Err; //modified
reg [2:0] y, Y;
reg of_Err, uf_Err; //added
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E =3'b100;
always #*
begin
if (Enable)
begin
case (y)
A: if (s == 3'b000)
Y = B;
else
begin
Y = A;
uf_Err = 1; //modified
end
B: if (s == 3'b000)
Y = C;
else if (s == 3'b001)
Y = A;
else
begin
Y = B;
uf_Err = 1; //modified
end
C: if (s == 3'b000)
Y = D;
else if (s == 3'b100)
Y = C;
else
Y = B;
D: if (s == 3'b000)
Y = E;
else if (s == 3'b100)
Y = D;
else Y = C;
E: if (s == 3'b000)
begin
Y = E;
of_Err = 1; //modified
end
else if (s == 3'b100) Y = E;
else Y = D;
default: Y = 3'bxxx;
endcase
c[1] = y[1];
c[0] = y[0];
end
else
begin
//write the condition if the Enable signal is not high.I guess you're trying to synthesize
end
end
always #(negedge Resetn, posedge Clock)
begin
if (Resetn == 0)
begin
y <= A;
// OF_Err = 0; //Problem
// UF_Err = 0; //Problem
end
else y <= Y;
end
assign OF_Err = !Resetn? of_Err : 1'b0; //added
assign UF_Err = !Resetn? uf_Err : 1'b0; //added
endmodule
As others have already pointed out, OF_Err and UF_Err were driver by two always blocks which is illegal for synthesis. I recommend creating two additional variables of_Err and uf_Err like Arvind suggested. However I recommend keeping OF_Err and UF_Err as flops.
The if (Enable) in the combinational block infers Y,c and the *_Err as level-sensitive latches. I highly doubt this is what you intendeds. I recommend moving the if (Enable) into synchronous always block and keeping the combinational logic as pure combinational.
c is a simple assignment, so it might make more sense having it as a wire instead of a reg with a simple assign statement. It can be in the combinational block, but I prefer to separate combinational input from output.
You did use #(s, y, Enable) correctly, however #* or the synonymous #(*) is recommenced for combinational block. #* is an auto sensitivity list which saves you typing, maintenance, and removes the risk of forgetting a signal.
always #*
begin
of_Err = OF_Err; // <-- default values
uf_Err = UF_Err;
case (y)
// ... your original case code with OF_Err/UF_Err renamed to of_Err/uf_Err
endcase
end
always #(posedge Clock, negedge Resetn) // style difference, I prefer the clock to be first
begin
if (Resetn == 1'b0)
begin
y <= A;
OF_Err <= 1'b0;
UF_Err <= 1'b0;
end
else if (Enable)
begin
y <= Y;
OF_Err <= of_Err;
UF_Err <= uf_Err;
end
end
assign c[1:0] = y[1:0];
Because OF_Err and UF_ERR are driven by multiple always blocks.
A reg should be driven by only one always block. And if it is having
multiple drivers by design, then it should be a wire.
Here is your modified code.
module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output reg OF_Err = 0, UF_Err = 0;
reg [2:0] y, Y;
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
always #(s, y, Enable, negedge reset)
begin
if (!reset)
begin
OF_Err = 0; //Problem
UF_Err = 0; //Problem
end
else
begin
if (Enable)
begin
case (y)
A: if (s == 3'b000) Y = B;
else
begin
Y = A;
UF_Err = 1;
end
B: if (s == 3'b000) Y = C;
else if (s == 3'b001) Y = A;
else
begin
Y = B;
UF_Err = 1;
end
C: if (s == 3'b000) Y = D;
else if (s == 3'b100) Y = C;
else Y = B;
D: if (s == 3'b000) Y = E;
else if (s == 3'b100) Y = D;
else Y = C;
E: if (s == 3'b000)
begin
Y = E;
OF_Err = 1;
end
else if (s == 3'b100) Y = E;
else Y = D;
default: Y = 3'bxxx;
endcase
c[1] = y[1];
c[0] = y[0];
end
end
end
always #(negedge Resetn, posedge Clock)
begin
if(Resetn == 0)
y <= A;
else
y <= Y;
end
I have the Verilog code shown below, and if I try to compile it I get an error message. The point is that I'm trying to manipulate an input, which as long as I know cannot be done in Verilog. The point is that I need check the following condition in Verilog:
static int prime(unsigned long long n)
{
unsigned long long val = 1;
unsigned long long divisor = 5;
if (n == 2 || n == 3)
return 1;
if (n < 2 || n%2 == 0 || n%3 == 0)
return 0;
for ( ; divisor<=n/divisor; val++, divisor=6*val-1)
{
if (n%divisor == 0 || n%(divisor+2) == 0)
return 0;
}
return 1;
}
At the moment I have the following code:
module prime(clk, rst, start, A, ready, P);
input clk, rst, start;
input [7:0] A;
output ready, P;
reg ready, P;
wire [7:0] divisor;
assign divisor = 5;
wire [7:0] val;
assign val = 1;
always # (posedge clk or posedge rst) begin
if (!rst) begin
P <= 0;
end
else if (start) begin
case (A)
0 : P <= 1;
1 : P <= 1;
2 : P <= 1;
3 : P <= 1;
endcase
if (A%2 == 0 && A != 2) begin
P <= 0;
end
else begin
for( ; divisor <= A/divisor; val=val+1, divisor=6*val-1) begin
if (A%divisor == 0 || A%(divisor+2) == 0) begin
P <= 0;
end
end
// need to set P to 1
end
end
end
endmodule
Please also note I need to test primes in the form of 6n+1 or 6n-1, and I also need to assume in my code that 0 and 1 are also primes.
If I try the above code I get an error message saying:
Enhanced FOR loop is not enabled for verilog
If anyone can help me solve the error and finish my logic in Verilog, I would be glad.
The Verilog BNF does not allow empty or compound statements in for(;;). Change the file to *.sv to compile it under SystemVerilog rules. Otherwise change your for loop statement to have simple statements
for( divisor =5; divisor <= A/divisor; divisor=6*val-1) begin
if (A%divisor == 0 || A%(divisor+2) == 0) begin
P <= 0;
end
val++;
end
Also, you can't make procedural assignments to wires. make them variables.
I want to write a module for GCD computing, using extended Euclidean algorithm. But the main problem is that I completely don't know how to do that without getting to the lowest (RTL) level. What I mean is to have FSM with three states:
IDLE (waiting for input)
COMPUTING (as many clock cycles as needed)
FINISHED (ready to read output).
However, when I try to separate FSM & computations into separate processes, like this:
module modinv(clk, reset, number, prime, finished, gcd, inverse_fail, inverse);
input [31:0] number, prime;
input wire clk, reset;
output integer gcd, inverse;
output reg finished, inverse_fail;
parameter [2:0] IDLE = 3'b001, COMPUTING = 3'b010, END = 3'b100;
reg [2:0] state, state_next;
integer a, b, c, q, p, r;
always # (posedge clk, posedge reset)
begin
if (reset == 1)
begin
state <= IDLE;
end
else
begin
state <= state_next;
end
end
always #(state or b)
begin
finished <= 0;
inverse_fail <= 0;
case (state)
IDLE:
begin
a <= number;
b <= prime;
p <= 1;
r <= 0;
state_next <= COMPUTING;
end
COMPUTING:
begin
c = a % b;
q = a / b;
a = b;
b = c;
r = p - q * r;
p = r;
if (b == 0)
begin
state_next <= END;
end
else
begin
state_next <= COMPUTING;
end
end
END:
begin
gcd <= a;
inverse <= p;
finished <= 1;
if (gcd != 1)
begin
inverse_fail <= 1;
end
end
endcase
end
endmodule
And when I try to put computation in the second process, in COMPUTING state case, it only works once - what is correct in means of verilog, because until computing is done, state doesn't change, so the process isn't called again.
However, when I put computation in the first process, there isn't any non-ugly way to limit the computations only to correct STATE, which results in wrong output (as soon as FSM is in FINISHED state, the output is already incorrect - one step further).
So, my question is - how to do it correctly without using FSM + datapath (low-level RTL) solution?
My current waveform:
You seem to be missing some clocked elements in your design.
From what I understand of your design, you seem to expect once the state goes to COMPUTING, it should keep iterating the values of a and b until b reaches 0. But the only thing you're actually clocking on a clock edge is the state variable, so there's no memory of a and b from one state to the next. If you want variables like a and b to have memory from one clock cycle to the next, then you need to latch these variables as well:
I made some modifications to your program, it might not be 100% correct, but you should see what I'm getting at. See if this makes sense how you do the combinational logic in the second block, but you register the values on the posedge so that you can use them at the start of the next clock cycle.
module modinv(clk, reset, number, prime, finished, gcd, inverse_fail, inverse);
input [31:0] number, prime;
input wire clk, reset;
output integer gcd, inverse;
output reg finished, inverse_fail;
parameter [2:0] IDLE = 3'b001, COMPUTING = 3'b010, END = 3'b100;
reg [2:0] state, state_next;
integer a, b, c, q, p, r;
integer a_next, b_next, p_next, r_next;
always # (posedge clk, posedge reset)
begin
if (reset == 1)
begin
state <= IDLE;
a <= 0;
b <= 0;
p <= 0;
r <= 0;
end
else
begin
state <= state_next;
a <= a_next;
b <= b_next;
p <= p_next;
r <= r_next;
end
end
always #* //just use the auto-triggered '#*' operator
begin
finished <= 0;
inverse_fail <= 0;
case (state)
IDLE:
begin
a_next <= number;
b_next <= prime;
p_next <= 1;
r_next <= 0;
state_next <= COMPUTING;
end
COMPUTING:
begin
c = a % b;
q = a / b;
a_next = b;
b_next = c;
r_next = p - q * r;
p_next = r;
if (b == 0)
begin
state_next <= END;
end
else
begin
state_next <= COMPUTING;
end
end
END:
begin
gcd <= a;
inverse <= p;
finished <= 1;
if (gcd != 1)
begin
inverse_fail <= 1;
end
end
endcase
end
endmodule
Ok so I know my code works for a 3 number sequence but for with the finite state machine model I drew out this should be correct but it doesn't work for a 4 number sequence. It only detects the first 3. I need to detect with an overlap "0110" from the sequence 01100110110111. It should have 3 "0110" sequences and 2 overlapping but when I run my Verilog it detects 4 "0110" sequences which tells me it's only grabbing "011" Can someone look at my code and see what I'm doing wrong? I could simply add another state but I wouldn't think that's the correct way since I don't have another state in my diagram.
module moore_seq
(
input clock, reset, x,
output reg z
);
//assign binary encoded codes to the states A through D
parameter A = 2'b00,
B = 2'b01,
C = 2'b10,
D = 2'b11;
reg [1:0] current_state, next_state;
//Section 1: Next state generator (NSG)
always#(*)
begin
casex(current_state) //ignore unknown and Hi-Z inputs
A: if (x == 1)
next_state = A;
else
next_state = B;
B: if (x == 1)
next_state = C;
else
next_state = B;
C: if (x == 1)
next_state = D;
else
next_state = B;
D: if (x == 1)
next_state = A;
else
next_state = B;
endcase
end
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == D)
z = 1;
else
z = 0;
end
//Section 3: The Flip Flops
always#(posedge clock, posedge reset)
begin
if(reset == 1)
current_state <= A;
else
current_state <= next_state;
end
endmodule
UPDATED:
parameter A = 3'b000,
B = 3'b001,
C = 3'b010,
D = 3'b011,
E = 3'b100;
reg [1:0] current_state, next_state;
//Section 1: Next state generator (NSG)
always#(*)
begin
casex(current_state) //ignore unknown and Hi-Z inputs
A: if (x == 1)
next_state = A;
else
next_state = B;
B: if (x == 1)
next_state = C;
else
next_state = B;
C: if (x == 1)
next_state = D;
else
next_state = B;
D: if (x == 1)
next_state = A;
else
next_state = E;
E: if (x == 1)
next_state = C;
else
next_state = B;
endcase
end
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == E)
z = 1;
else
z = 0;
end
I suppose, four states is enough. Just change
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == D)
to
//Section 2: Output Generator (OG)
always#(*)
begin
if(current_state == D && x == 0 )