I have tried to build linux-0.11.
And I found that the makefile in linux-0.11 contains :
.c.s:
#$(CC) $(CFLAGS) -S -o $*.s $<
.s.o:
#$(AS) -o $*.o $<
.c.o:
#$(CC) $(CFLAGS) -c -o $*.o $<
Could anyone tell me that what does .c.s:, .s.o: and .c.s: mean?
Thanks!
Those are suffix rules. They are a more primitive and limited (but standards conforming) form of pattern rules.
The rule .c.o means "if you have a foo.c, you can turn it into a foo.o with this recipe". Ditto for the others.
Related
I'm compiling a 8051 project with SDCC but has a problem with Makefile, the following sources:
TARGET = test
CC = sdcc
CFLAGS = -Wall -I.
RM = rm -rf
SRCS = $(wildcard *.c)
RELS = $(patsubst %.c,%.rel,$(SRCS))
$(TARGET).bin: $(TARGET).hex
objcopy -I ihex -O binary $< $#
$(TARGET).hex: $(TARGET).ihx
packihx $< > $#
$(TARGET).ihx: $(RELS)
#echo Linking ...
$(CC) $(CFLAGS) $< -o $#
#echo Build finish!
%.rel: %.c
#echo Compiling ...
$(CC) $(CFLAGS) -c $< -o $#
.PHONY: clean
clean:
#echo Removing ...
$(RM) *.rel *.ihx *.lk *.lst *.map *.mem *.rst *.sym *.asm $(TARGET)
#echo Removed!
When I run make it has errors:
minh#PCDESIGN:~/workspaces/programMSC51/test$ make
Compiling ...
sdcc -Wall -I. -c main.c -o main.rel
sdas Assembler V02.00 + NoICE + SDCC mods (Intel 8051)
Copyright (C) 2012 Alan R. Baldwin
This program comes with ABSOLUTELY NO WARRANTY.
Usage: [-Options] file
Usage: [-Options] outfile file1 [file2 file3 ...]
-d Decimal listing
-q Octal listing
-x Hex listing (default)
-g Undefined symbols made global
-a All user symbols made global
-b Display .define substitutions in listing
-bb and display without .define substitutions
-c Disable instruction cycle count in listing
-j Enable NoICE Debug Symbols
-y Enable SDCC Debug Symbols
-l Create list file/outfile[.lst]
-o Create object file/outfile[.rel]
-s Create symbol file/outfile[.sym]
-p Disable automatic listing pagination
-u Disable .list/.nlist processing
-w Wide listing format for symbol table
-z Disable case sensitivity for symbols
-f Flag relocatable references by ` in listing file
-ff Flag relocatable references by mode in listing file
-I Add the named directory to the include file
search path. This option may be used more than once.
Directories are searched in the order given.
removing
make: *** [Makefile:22: main.rel] Error 1
How can I fix this?
Unlike other compilers, SDCC does not have a -Wall option. You should remove it from CFLAGS = -Wall -I. in the Makefile.
It also does not have a replacement. There are options --less-pedantic and -Werror, which gives you fewer warnings, or treats warnings as errors, respectively, but there is no option for creating more warnings.
The manual mentions --more-pedantic, but
Actually this is not a SDCC compiler option but if you want more warnings you can use a separate tool dedicated to syntax checking [...]
See SDCC Compiler User Guide (version 4.1.12), section 3.3.4.
I have the following makefile. It works well for .f and .c files but when I have .f90 file and want to compile it with ifort does not work?
Could you please advise me where I should change and how?
Thanks you
FCOMPFLAGS = -O -ffixed-line-length-132
CCOMPFLAGS = -O
FFLAGS = $(FCOMPFLAGS) -fsecond-underscore
CFLAGS = $(CCOMPFLAGS)
LDFLAGS = $(FCOMPFLAGS)
LD = gfortran
FC = gfortran
MAKEFILE = Makefile
PROGRAM1 = f1
OBJS = f1.o \
f2.o \
f3.o
all: $(PROGRAM1)
$(PROGRAM1): $(OBJS) $(MAKEFILE)
$(LD) $(LDFLAGS) $(OBJS) -o $(PROGRAM1)
clean: #rm -f $(OBJS) core
when I execute "make" I get the following error,
make: *** No rule to make target `f1.o', needed by `f90_simple'. Stop.
It seems that My makefile does not recognize *.f90 files, and my other question is do we have flag for ifrot compiler to be used in makefile
Thanks
You need to add the implicit rule:
%.o : %.f90
<tab>$(FC) $(FCOMPLAGS) -c $<
I have an error while making my makefile in linux. Here's my code:
CC = gcc
CFLAGS = -Wall -m32 -g -fno-stack-protector -z execstack -O0
SHELL_SOURCES = Shell.c
SHELL = Shell
.PHONY: all target1 clean
all: target1
target1: $(SHELL)
$(SHELL): $(SHELL_SOURCES)
$(CC) $(CFLAGS) $^ -o $#
clean:
rm -rf $(SHELL)
The error I get is:
gcc -Wall -m32 -g -fno-stack-protector -z execstack -O0 Shell.c -o Shell
make: Shell: Command not found
Makefile:16: recipe for target 'Shell' failed
make: *** [Shell] Error 127
You can't use SHELL as a variable in a Makefile, it is used to know what shell (/bin/sh, /bin/bash, etc) will be used in your Makefile.
CC = gcc
CFLAGS = -Wall -m32 -g -fno-stack-protector -z execstack -O0
EXE_SOURCES = Shell.c
EXE = Shell
.PHONY: all target1 clean
all: target1
target1: $(EXE)
$(EXE): $(EXE_SOURCES)
$(CC) $(CFLAGS) $^ -o $#
clean:
rm -rf $(EXE)
Take more time to read documentation of GNU make
You should remove spaces around variable assignments, e.g. code
CC= gcc
Beware that tab characters are significant in Makefile-s (in rules, for their action lines). Use some editor aware of that (e.g. emacs has a mode for Makefile). See also this example (but the rule action should really start with a tab character). Notably, you need a tab just before the $(CC) $(CFLAGS) $^ -o $# and another one before rm.
Consider also using remake -x to debug your Makefile, or at least make --trace
But the main bug was indeed, as answered by Cpatricio, to use the SHELL variable. Be careful when using variables or names already known to make. Actually, I have the habit of prefixing my make variable names with a common prefix, so you could have defined your variables like JOJOIGA_SOURCES=$(wildcard *.c), JOJOIGA_SHELL=Shell etc....
I have a makefile that looks like this:
CS := a.c b.c
CPPS := foo.cpp bar.cpp
SOURCES := $(CS) $(CPPS)
OBJS := $(CS:%.c=$(OBJSDIR)/%.o) $(CPPS:%.cpp=$(OBJSDIR)/%.o)
I want to create a single rule to compile them all. But the only option I can think of is this:
$(OBJSDIR)/%.o: %.cpp
$(GXX) $(GXXFLAGS) -c $< -o $#
But of course it doesn't work because some of the object files don't have a matching C++ source file.
Any idea?
suppose you have a.cc, b.cc and c.cc, and on the other side, d.c, e.c and f.c
program_objs = a.o b.o c.o d.o e.o f.o
program: $(program_objs)
$(CC) $(LDFLAGS) -o $# $(program_objs)
You don't need anything more, as make will automatically detect which files are c++ and which ones are plain c and will select the proper compiler.
in case you want something special, not included in makefile, you can add some suffixes (file types) with the rule:
.SUFFIXES: .a .b .o
and then use the following rules to compile them to .o
.a.o:
$(COMPILER_A) $(COMPILER_A_FLAGS) -c $# -o $<
.b.o:
$(COMPILER_B) $(COMPILER_B_FLAGS) -c $# -o $<
and let makefile select the proper compiler (the one stored in variables COMPILER_A or COMPILER_B) to do the work.
Of course, you can compile something to a .o file with an explicit rule, as in:
a.o: a.cc
g++ -o a.o -c a.cc
b.o: b.cc
g++ -o b.o -c b.cc
c.o: c.cc
g++ -o c.o -c c.cc
d.o: d.c
gcc -o d.o -c d.c
e.o: e.c
gcc -o e.o -c e.c
f.o: f.c
gcc -o f.o -c f.c
Note #1:
Some sugestions have been made on GNU make % pattern to construct implicit rules for targets. Below is a rewritting of the implicit rules above to do the same thing:
%.o: %.a
$(COMPILER_A) $(COMPILER_A_FLAGS) -c $# -o $<
%.o: %.b
$(COMPILER_B) $(COMPILER_B_FLAGS) -c $# -o $<
As always, $# means the target of the rule and $< (you can use also $* for the file name without any matching suffixes) the left needed file. For a complete list of automatic variables that can be used, I suggest you to read your make manual. Take into account that the old suffix syntax is reversed from the new one (the target suffix appears last in the old syntax, the new syntax being more similar to a normal makefile rule with the target on the left side of the colon)
I want to create a single rule to compile them all.
As Etan Reisner said in the comment section, make already has implicit rules to compile .c and .cpp file, so the real answer to your question is:
Do not write anything to compile your object files.
That said, you should now remove those two variables: $(GXX) and $(GXXFLAGS).
To provide flags to cc or gcc one should use the CFLAGS built-in variable.
To provide flags to g++ one should use the CXXFLAGS built-in variable.
To provide flags to the preprocessor (cpp) one should use the CPPFLAGS variable.
Since you're mixing C and C++ source files, you should use the CXX variable as the linker command.
I have written a Makefile which works fine; I do not post it entirely, just the part of it under investigation:
COMPILE_cpp = $(CXX) $(CFLAGS) -o $# -c $< $(MAKEDEP) $(INCLUDES)
%.o : %.cpp ; $(COMPILE_cpp)
.SUFFIXES: .o .cpp
The above code does its duty. Since the build process involves many files I would like to add some color output. I have tried the following
PRINT = #echo -e "\e[1;34mBuilding $<\e[0m"
COMPILE_cpp = $(PRINT) && $(CXX) $(CFLAGS) -o $# -c $< $(MAKEDEP) $(INCLUDES)
%.o : %.cpp ; $(COMPILE_cpp)
.SUFFIXES: .o .cpp
The Makefile still works fine but now I can only see the output of $(PRINT) with the chosen color. The command string $(CXX) $(CFLAGS) -o $# -c $< $(MAKEDEP) $(INCLUDES) is correctly executed but not printed to screen any more; still I can see the eventual warnings and errors.
I would like to avoid using external tools (such as colorgcc or CMake) and hack it with bash script tricks.
Thanks in advance!
EDIT
Just a little add: what about if I want to do something like grep the output of the current built file in order to find strings such as error or warning?
I would like to highlight them, I was thinking about calling a sed on the compiler output to change some words color...
The # symbol at the start of your PRINT definition is suppressing the command printing.
Try this:
%o : %.cpp
$(PRINT)
$(COMPILE_cpp)
where $(COMPILE_cpp) is your first version.
Dont forget the tab character indents recipe commands, not spaces.