verilog why doesn't it make proper result in register file? - verilog

Question

i'm making 8x32b register file below is my verilog code
module register_file(clk, reset, dstW, valW, write, srcA, srcB, valA, valB );
input clk;
input reset;
input[2:0] dstW;
input[31:0] valW;
input write;
input[2:0] srcA;
input[2:0] srcB;
output[31:0] valA;
output[31:0] valB;
reg[31:0] r0eax, r1ecx, r2edx, r3ebx, r4esi, r5edi, r6esp, r7edi;
wire[31:0] reg_input_0, reg_input_1, reg_input_2, reg_input3, reg_input4,
reg_input5, reg_input6, reg_input7;
wire[7:0] decoder_out, select;
assign valA =
(srcA == 3'b000) ? r0eax:
(srcA == 3'b001) ? r1ecx:
(srcA == 3'b010) ? r2edx:
(srcA == 3'b011) ? r3ebx:
(srcA == 3'b100) ? r4esi:
(srcA == 3'b101) ? r5edi:
(srcA == 3'b110) ? r6esp:
(srcA == 3'b111) ? r7edi: 32'bx;
assign valB =
(srcB == 3'b000) ? r0eax:
(srcB == 3'b001) ? r1ecx:
(srcB == 3'b010) ? r2edx:
(srcB == 3'b011) ? r3ebx:
(srcB == 3'b100) ? r4esi:
(srcB == 3'b101) ? r5edi:
(srcB == 3'b110) ? r6esp:
(srcB == 3'b111) ? r7edi: 32'bx;
assign decoder_out[0] = (dstW == 3'b000)? 1'b1 : 1'b0;
assign decoder_out[1] = (dstW == 3'b001)? 1'b1 : 1'b0;
assign decoder_out[2] = (dstW == 3'b010)? 1'b1 : 1'b0;
assign decoder_out[3] = (dstW == 3'b011)? 1'b1 : 1'b0;
assign decoder_out[4] = (dstW == 3'b100)? 1'b1 : 1'b0;
assign decoder_out[5] = (dstW == 3'b101)? 1'b1 : 1'b0;
assign decoder_out[6] = (dstW == 3'b110)? 1'b1 : 1'b0;
assign decoder_out[7] = (dstW == 3'b111)? 1'b1 : 1'b0;
and(select[0], write, decoder_out[0]);
and(select[1], write, decoder_out[1]);
and(select[2], write, decoder_out[2]);
and(select[3], write, decoder_out[3]);
and(select[4], write, decoder_out[4]);
and(select[5], write, decoder_out[5]);
and(select[6], write, decoder_out[6]);
and(select[7], write, decoder_out[7]);
assign reg_input_0 = select[0] ? valW : r0eax;
assign reg_input_1 = select[1] ? valW : r1ecx;
assign reg_input_2 = select[2] ? valW : r2edx;
assign reg_input_3 = select[3] ? valW : r3ebx;
assign reg_input_4 = select[4] ? valW : r4esi;
assign reg_input_5 = select[5] ? valW : r5edi;
assign reg_input_6 = select[6] ? valW : r6esp;
assign reg_input_7 = select[7] ? valW : r7edi;
always #(posedge clk or negedge reset)
begin
if(!reset) begin
r0eax <= 32'b0;
r1ecx <= 32'b0;
r2edx <= 32'b0;
r3ebx <= 32'b0;
r4esi <= 32'b0;
r5edi <= 32'b0;
r6esp <= 32'b0;
r7edi <= 32'b0;
end
else begin
r0eax <= reg_input_0;
r1ecx <= reg_input_1;
r2edx <= reg_input_2;
r3ebx <= reg_input_3;
r4esi <= reg_input_4;
r5edi <= reg_input_5;
r6esp <= reg_input_6;
r7edi <= reg_input_7;
end
end
endmodule
and testbench is as follows
module tttt;
// Inputs
reg clk;
reg reset;
reg [2:0] dstW;
reg [31:0] valW;
reg write;
reg [2:0] srcA;
reg [2:0] srcB;
// Outputs
wire [31:0] valA;
wire [31:0] valB;
integer i;
// Instantiate the Unit Under Test (UUT)
register_file uut (
.clk(clk),
.reset(reset),
.dstW(dstW),
.valW(valW),
.write(write),
.srcA(srcA),
.srcB(srcB),
.valA(valA),
.valB(valB)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
dstW = 0;
valW = 0;
write = 0;
srcA = 0;
srcB = 0;
i =0;
#10
reset = 0;
#10
reset = 1;
// Wait 100 ns for global reset to finish
#100;
clk=1;
valW = 100;
write = 1;
for(i=0; i<8; i = i+1) begin
clk =0;
#10;
dstW = i;
clk = 1;
#10;
clk =0;
#10;
valW = valW + 10;
clk =1;
#10;
end
#100;
write =0;
for(i=0; i<8; i=i+1 ) begin
clk = 0;
#10;
srcA = i;
srcB = i;
#10;
clk=1;
#10;
end
clk =0;
#10;
clk = 1;
// Add stimulus here
end
endmodule
and result
it just results 0 value after third i value.
i checked using red rectangular. could you give me a advice ? thanks in advance

Answer 1

When you synthetize your design, these warnings show up:
WARNING:Xst:1780 - Signal <reg_input7> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <reg_input6> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <reg_input5> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <reg_input4> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <reg_input3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
If the synthetizer detects that those signals are not being used, it discards them. Note that these signals affect the selection of registers 3 to 7, and because of that, you cannot see the loaded value when you read them.
But... your code assigns and use these signals, doesn't it?
assign reg_input_0 = select[0] ? valW : r0eax;
assign reg_input_1 = select[1] ? valW : r1ecx;
assign reg_input_2 = select[2] ? valW : r2edx;
assign reg_input_3 = select[3] ? valW : r3ebx;
assign reg_input_4 = select[4] ? valW : r4esi;
assign reg_input_5 = select[5] ? valW : r5edi;
assign reg_input_6 = select[6] ? valW : r6esp;
assign reg_input_7 = select[7] ? valW : r7edi;
What makes reg_input_0,1 and 2 different from reg_input_3,4,5,6 and 7 ? This:
wire[31:0] reg_input_0, reg_input_1, reg_input_2, reg_input3, reg_input4,
reg_input5, reg_input6, reg_input7;
Look: reg_input_0, reg_input_1 and reg_input_2. Then, reg_input3 (where's the underscore??)
As reg_input_3 to reg_input_7 are not defined, they default to a 1-bit signal, instead of 32 bits. When you use the multiplexer, at reg_input_3 for instance, to define its value...
assign reg_input_3 = select[3] ? valW : r3ebx;
You are actually synthetizing this:
assign reg_input_3 = select[3] ? valW[0] : r3ebx[0];
And in your clocked always, the actual register assignment is not as this:
r3ebx <= reg_input_3;
But as this:
r3ebx[0] <= reg_input_3;
This description of yours causes feedback from the register output through the input via the mentioned multiplexor. While this is ok when the there's a clock triggered register, if the synthetizer doesn't detect it, you will end up generating a lot of unnecesary multiplexers. Look at this generated schematic from the results of the synthesis process (synthetizer is XST)
The eight squares at the right are your eight registers. At the left, there are a massive amount of multiplexers. I cannot show you all of them, because the generated schematic it's too large for screen capture.
I suggest not to use an explicit loopback path with the multiplexor to decide when to write a new value to the register. Instead of that, modify your synchronous always to load a new value into the register only if that register is selected for writting:
always #(posedge clk or negedge reset)
begin
if(!reset) begin
r0eax <= 32'b0;
r1ecx <= 32'b0;
r2edx <= 32'b0;
r3ebx <= 32'b0;
r4esi <= 32'b0;
r5edi <= 32'b0;
r6esp <= 32'b0;
r7edi <= 32'b0;
end
else begin
if (select[0])
r0eax <= valW;
if (select[1])
r1ecx <= valW;
if (select[2])
r2edx <= valW;
if (select[3])
r3ebx <= valW;
if (select[4])
r4esi <= valW;
if (select[5])
r5edi <= valW;
if (select[6])
r6esp <= valW;
if (select[7])
r7edi <= valW;
end
end
This description allows the synthetizer to infer a register with CLK and CE inputs: the register will accept a new value from its D input if CE is enabled. If not, the value doesn't change. Your description makes the register to change its value on every clock cycle, whether is needed or not.
Now the circuit inferred is as this (it actually fits on screen!):
With this proposed solution, the first block, where the different reg_input_X signals are assigned, can be eliminated.
Tested using ISIM with ISE Webpack 12.4 and works :)