The objective is to write structural Verilog code for a circuit that has two inputs, w1 and w2, and an output, q. The circuit compares the input sequences of w1 and w2. If w1 and w2 match for 4 consecutive clock pulses, q should be 1; otherwise it should remain at 0.
Example:
w1 = 0100111010010
w2 = 0000110010010
q = 0000010000111
I've drawn a state diagram and a state table and concluded that I need 3 D flip flops for this circuit. I then wrote K-maps for the inputs of each D-FF. However, when I wrote the code, the resulting waveform unexpectedly looks like this:
Here is my code:
module PatternMatch2(q, w1, w2, clk, rst);
output q;
input w1, w2, clk, rst;
DF DF1(y1, yBar1, Y1, clk, rst),
DF2(y2, yBar2, Y2, clk, rst),
DF3(y3, yBar3, Y3, clk, rst);
and and0(Y1, nI, yBar3, yBar1),
and1(Y2In1, nI, yBar2, y1),
and2(Y2In2, nI, y2, yBar1),
and3(Y3In1, nI, y3),
and4(Y3In2, nI, y2, y1),
and5(q, y3, yBar2, yBar1);
xor xor0(i, w1, w2);
or or0(Y2, Y2In1, Y2In2),
or1(Y3, Y2In1, Y2In3);
not not0(nI, i);
endmodule
// D - Flip Flop Module
module DF(q, qBar, D, clk, rst);
input D, clk, rst;
output q, qBar;
reg q;
not n1 (qBar, q);
always# (posedge rst or posedge clk)
begin
if(rst)
q = 0;
else
q = D;
end
endmodule
I'm not sure what's wrong in my code as my equations seem correct.
When I compile your code, I get this warning message:
Implicit wire 'Y2In3' does not have any driver
You need to drive your or1 input appropriately.
You only need 2 FFs organized as a saturating counter with reset for such task:
Create a reset signal rst=XOR(w1,w2) and connect to both FF's reset input
Connect your FFs inputs (d0, d1) to outputs (q0, q1) according to a following truth table (2-bit counter with saturation):
q1 q0 => d1 d0
0 0 => 0 1
0 1 => 1 0
1 0 => 1 1
1 1 => 1 1
That is:
d0 = OR(NOT(q0), q1)
d1 = OR(q0, q1)
Your output will be: q=AND(q0, q1, NOT(rst))
Related
I have to make a 64 Bit ALU that takes in A and B 64-bit inputs, a carry_in input and outputs a 64bit result along with a 1-bit carry_out. There is also a 5 bit function-select FS. Where FS[0] controls whether B is inverted or not (using a 2to1 mux.) F[1] does the same for the A. And FS[4:2] determines which operation (Adding, subtracting, logical operations, etc) using an 8to1 Mux. Below is the code for the ALU and Testbench.
I'm pretty sure my testbench is good and so is all the separate components for the ALU. I'm not too confident about my top-level where I instantiate and connect all the inputs/outputs. What is causing the high impedance in the waveform?
module ALU(A, B, FS, cin, cout, result);
input [63:0] A, B;
input [4:0] FS;
input cin;
output cout;
output [63:0] result;
eight_one_mux u7 (firstoutA & secoutB, firstoutA | secoutB, sum, firstoutA ^ secoutB,
left, right, 1'b0, 1'b0, FS[4:2], result);
adder u6 (firstoutA, secoutB, cin, sum, cout);
firstmux u1 (A, !A, FS[1], firstoutA);
secmux u2 (B, !B, FS[0], secoutB);
Alu_shifter u5 (A, left, right);
endmodule
//--------------------------------------------------------------------------------//
//These are the two muxes to split into input and inverted input A,B
module firstmux(a, nota, firstS, firstoutA);
input [63:0] a, nota;
input firstS;
output reg [63:0] firstoutA;
always #(a or nota or firstS)
begin
case(firstS)
0 : firstoutA = a;
1 : firstoutA = nota;
default : firstoutA = 1'bx;
endcase
end
endmodule
//<><><><><><><>//
module secmux(b, notb, secS, secoutB);
input [63:0] b, notb;
input secS;
output reg [63:0] secoutB;
always #(b or notb or secS)
begin
case(secS)
0 : secoutB = b;
1 : secoutB = notb;
default : secoutB = 1'bx;
endcase
end
endmodule
//--------------------------------------------------------------------------------//
//This is the Shifter Blocks
module Alu_shifter (shiftA, right, left); //This shifter block shifts the A input once right or left
input [63:0] shiftA;
output [63:0] right;
output [63:0] left;
shift_right w1 ( //instantiate right shifter block
.a_R(shiftA),
.R(right)
);
shift_left w2 ( //instantiate left shifter block
.a_L(shiftA),
.L(left)
);
endmodule
////////><><><><><><><><><><><><><><><///////
module shift_right (a_R, R); // right shifter block
input [63:0] a_R;
output [63:0] R;
assign R = a_R >> 1; //shift A right once (shift in a 0)
endmodule
module shift_left (a_L, L); //left shifter block
input [63:0] a_L;
output [63:0] L;
assign L = a_L << 1; //shift A left once (shift in a 0)
endmodule
//End shifter blocks (3 total modules)
//----------------------------------------------------//////////////////////
//This is the Adder that Adds A, B and cin
module adder(addA, addB, nic, sum, cout);
input [63:0] addA, addB;
input nic;
output [63:0] sum;
output cout;
assign {cout, sum} = addA + addB + nic;
endmodule
//----------------------------------------------------//////////////////////
//This is the 8to1 Mux that decides which operation is put forward
module eight_one_mux(D0, D1, D2, D3, D4, D5, D6, D7, S, out);
input [63:0] D0, D1, D2, D3, D4, D5, D6, D7;
input [2:0] S;
output reg [63:0] out;
always #(D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7 or S)
begin
case(S)
0 : out = D0; //And
1 : out = D1; //Or
2 : out = D2; //Adder
3 : out = D3; //xor
4 : out = D4; //lefter
5 : out = D5; //righter
6 : out = D6; //GND
7 : out = D7; //GND
default : out = 1'bx;
endcase
end
endmodule
////////////-------------------------------////////////////////////////////
module ALU_tb();
reg [63:0] A, B;
reg [4:0] FS;
reg cin;
wire cout;
wire [63:0] result;
ALU dut (
.A(A),
.B(B),
.FS(FS),
.cin(cin),
.cout(cout),
.result(result)
);
initial begin
A = 8'b11001100;
B = 8'b11001101;
FS = 5'b01101;
cin = 1;
end
always
#5 cin <= ~cin;
always begin
#5
A <= A + 1;
B <= B + 2;
#5;
end
initial begin
#100 $finish;
end
endmodule
```
Unexpected high impedance (z) values are typically the result of undriven signals, and that is the problem with your code.
adder u6 (firstoutA, secoutB, cin, sum, cout);
In the line above, you connect the 1-bit signal firstoutA to the 64-bit addA input port. This connects firstoutA to addA[0], leaving the other 63 bits undriven. Thus, addA[63:1] are all z.
firstoutA is a 1-bit signal because you did not explicitly declare it. Also, undeclared signals are assumed to be of type wire, which default to z.
It is good practice to declare all signals.
To find all undeclared signals, add this to the top of your code:
`default_nettype none
You should get compile errors like:
Error-[IND] Identifier not declared
Identifier 'firstoutA' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
Error-[IND] Identifier not declared
Identifier 'secoutB' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
First you need to define signals (wire) for connections between modules. For example, you have left and right as outputs of Alu_shifter module and they are connected to firstmux and secmux modules; however, they are not defined in your top module. You should add following signal definitions to your topmodule:
wire [63:0] left,right;
wire [63:0] firstoutA;
wire [63:0] secoutB;
wire [63:0] sum;
Also, eight_one_mux module takes eight 64-bit inputs. However, you set the last two of them as 1'b0. You should change them to 64'b0 as below.
eight_one_mux u7 (firstoutA & secoutB, firstoutA | secoutB, sum, firstoutA ^ secoutB,
left, right, 64'b0, 64'b0, FS[4:2], result);
Finally, !A does not invert all bits of A (same for B). It applies a reduction operation and generates a 1-bit signal (and firstmux module expects a 64-bit signal in its second input port).
I'd like to know how I could go about using AND, OR and other gates for multiple bits inputs. I was trying to build a 2:1 MUX but I got this error:
Expression width 2 does not match width 1 of logic gate array port 1.
Here's the code
module mux_21 #(parameter width = 1) (
input [width-1:0] d0, d1,
input s,
output [width-1:0] y
);
wire [width-1:0] ns, y1, y2;
not g1 (ns, s);
and g2 (y1, d0, ns);
and g3 (y2, d1, s);
or g4 (y, y1, y2);
endmodule
Primitive gates are always single bit. You need to create instance for each bit combination.
The most common way to is with a generate for-loop. Generate logic goes through static unrolled during the elaboration phase of compile.
genvar gidx;
wire ns;
wire [width-1:0] y1, y2;
not g1 (ns, s);
generate
for(gidx=0; gidx<width; gidx=gidx+1) begin : mux
and g2 (y1[gidx], d0[gidx], ns );
and g3 (y2[gidx], d1[gidx], s );
or g4 (y[gidx], y1[gidx], y2[gidx] );
end
endgenerate
You could also create a range of instances. This is a feature that has existed longer then the generate construct but less commonly used and I notices some synthesizers don't support it (ex Yosys 0.9 on EDAplayground).
wire ns;
wire [width-1:0] y1, y2;
not g1 (ns, s);
and g2 [width-1:0] (y1, d0, ns);
and g3 [width-1:0] (y2, d1, s);
or g4 [width-1:0] (y, y1, y2);
I am trying to pipeline a module which consists of 5 multipliers and 5 adders connected in series. The module is a polynomial calculator. Without pipelining the module is working perfectly so far.
multipliers [31:0] m0,m1,m2,m3,m4; // separate module
adders [31:0] a0,a1,a2,a3,a4; // separate module
user_input [31:0] input; // register
constants [31:0] c0,c1,c2,c3,c4; // registers
pipeliners [31:0] p0,p1,p3,p4,p4; // pipelining resisters
wires [31:0] w0,w1,w2,w3,w4; // wires
Without pipelining the structure looks like following,
[input]*[c0] => w0 => [w0]+[c1] => w1 => [w1]*[input] => w2 => [w2]+[c2] => w3 ... //goes on like this
As all of them are connected in series, the critical path consists of 10 components.
My implemented pipelining idea is following,
[input]*[c0] => w0 => p0 => [p0]+[c1] => w1 => p1 => [p1]*[input] => w2=> p2 => [p2]+[c2] => w3 ... //goes on like this
I have an error, "cannot be driven by primitives or continuous assignment."It is due to p0,p1,p3 ... registers. Converting them into wire solves the error but then they are not registers anymore. I am using iverilog as compiler.
My question is, how can I do the pipelining so that I get the output using least possible clock cycles and resolve the error as well?
******* Edited version with code *******
`timescale 1ns / 1ps
module poly (
clk,
q,
result
);
input clk;
input [31:0] q; //user input
output [31:0] result;
reg [31:0] c,c0,c1,c2,c3,c4;
reg [31:0] p, p0, p1, p2, p3, p4, p5, p6,p7,p8,p9,p10,p11,p12;
always #(q)
if (q>=32'h08000000 && q<32'h0A000000) begin
c <= 32'h058B90C0;
c0 <= 32'h74599F60;
c1 <= 32'h79481740;
c2 <= 32'h445B7440;
c3 <= 32'h5AF892E0;
c4 <= 32'h9E2C2258;
end else if (q>=32'h0A000000 && q<32'h0C000000)
begin
c <= 32'h258B90C0;
c0 <= 32'hFB942240;
c1 <= 32'h21558EC0;
c2 <= 32'h5D882000;
c3 <= 32'h75F846E8;
c4 <= 32'hF48F5786;
end
wire [31:0] x0,x1,x2,x3,x4;
wire [31:0] y0,y1,y2,y3,y4;
multiplier m4 (.i_multiplicand(q),.i_multiplier(c4),.o_result(x4));
assign = x4;
adder a4 (.a(p0),.b(c3),.c(y4));
assign p1 = y4;
assign p2 = q;
multiplier m3 (.i_multiplicand(p2),.i_multiplier(p1),.o_result(x3));
assign p3 = x3;
adder a3 (.a(p3),.b(c2),.c(y3));
assign p4 = y3;
assign p5 = q;
multiplier m2 (.i_multiplicand(p5),.i_multiplier(p4),.o_result(x2));
assign p6 = x2;
adder a2 (.a(p6),.b(c1),.c(y2));
assign p7 = y2;
assign p8 = q;
multiplier m1 (.i_multiplicand(p8),.i_multiplier(p7),.o_result(x1));
assign p9 = x1;
adder a1 (.a(p9),.b(c0),.c(y1));
assign p10 = y1;
assign p11 = q;
adder a0 (.a(p10),.b(p11),.c(y0));
assign p12 = y0;
multiplier m0 (.i_multiplicand(p12),.i_multiplier(c),.o_result(x0));
assign result = x0;
endmodule
As Morgan already stated you get only registers if you have a reg and a clock.
always #(posedge clk)
begin
p1 <= y4;
p2 <= q;
// etc.
end
Which if you think about it is rather obvious as this is a register:
Which as you can see has as input a signal and a clock.
module try2(p,d,q1,q2,q3,q4,q5,q6,q7,q8,c,a);
input p,c;
output [15:0]q1,q2,q3,q4,q5,q6,q7,q8,d,a;
reg [15:0] d=16'b0;//may be error
reg [15:0]a;
always # (posedge p) begin
d<=d+1;
end
DFF dff0(q1,d,p);
DFF dff1(q2,q1,p);
DFF dff2(q3,q2,p);
DFF dff3(q4,q3,p);
DFF dff4(q5,q4,p);
DFF dff5(q6,q5,p);
DFF dff6(q7,q6,p);
DFF dff7(q8,q7,p);
always # ( posedge c )begin
a = ( q1 + q2 + q3 + q4 + q5 + q6 + q7 + q8 )/8;
end
endmodule
module DFF(q,d,clk);
input [15:0]d;
input clk;
output [15:0]q;
reg [15:0]q;
always # (posedge clk)begin
q <=d;
end
endmodule
Here I am counting the high of pulse p and showing the value in 16 bit d.
And whenever another input c goes from 0 to 1 I am showing the average of last 8 values of d.
Problem:Here everything is working fine but the average value showing deviation of 1 and program is stimulating but not synthesizing .
Depending on which synthesis tool you are using, you may not use a variable initialization. You may need to use a reset signal. You can even make it synchronous with
always # (posedge p) begin
d<=reset ? 0 :d+1;
end
I am creating an adder and accumulator using structural only. Below is what I have do far:
module adder_and_accum(add, clb, clc, iac, x2, in, acc, carry, carrynot, qn2, qn3, qn4, qn5);
input add, clb, clc, iac, x2;
input [3:0] in;
output [3:0] acc;
output carry, carrynot, qn2, qn3, qn4, qn5;
wire adder1in2, adder2in2, adder3in2, adder4in2;
wire sum1, sum2, sum3, sum4;
wire ffin1;
wire cinadder1, cinadder2, cinadder3;
wire carrynot, clearcarry;
four_to_one_mux mux1(0, 0, in[3], 0, add, iac, adder1in2);
four_to_one_mux mux2(0, 0, in[2], 0, add, iac, adder2in2);
four_to_one_mux mux3(0, 0, in[1], 0, add, iac, adder3in2);
four_to_one_mux mux4(0, 1, in[0], 0, add, iac, adder4in2);
full_adder f1(sum1, ffin1, cinadder1, acc[3], adder1in2);
full_adder f2(sum2, cinadder1, cinadder2, acc[2], adder2in2);
full_adder f3(sum3, cinadder2, cinadder3, acc[1], adder3in2);
full_adder f4(sum4, cinadder3, 0, acc[0], adder4in2);
or(clearcarry, clc, clb);
d_flip_flop dff1(ffin1, x2, carry, carrynot, clc);
d_flip_flop dff2(sum1, x2, acc[3], qn2, clearcarry);
d_flip_flop dff3(sum2, x2, acc[2], qn3, clearcarry);
d_flip_flop dff4(sum3, x2, acc[1], qn4, clearcarry);
d_flip_flop dff5(sum4, x2, acc[0], qn5, clearcarry);
endmodule
Here are the Flip flop, mux, and full adder headers:
module full_adder(sum, cout, cin, inp1, inp2);
module four_to_one_mux(in0, in1, in2, in3, select0, select1, out);
module d_flip_flop(d, clk, q, qn, reset);
Flip flops, muxes, and full adder are modules I created and I know they work because I have tested them individually. They all show correct waveforms.
I have narrowed down the problem to the flip flop Q output being wrapped around back into my adder input. My ACC bus output just shows XXXX.
How do I tie the output for my flip flops back as an input into my adder?
Here is the schematic of the adder and accumulator I made for reference.
Switching to the built in flip flop in xilinx fixed the issue:
FDRE FDRE_inst (
.Q(acc[0]), // 1-bit Data output
.C(x2), // 1-bit Clock input
.CE(ce), // 1-bit Clock enable input
.R(clb), // 1-bit Synchronous reset input
.D(sum4) // 1-bit Data input
);
I was able to just use a wire to tie the outputs of the flip flop back into the 4 bit adder. Nothing special was required.