module try2(p,d,q1,q2,q3,q4,q5,q6,q7,q8,c,a);
input p,c;
output [15:0]q1,q2,q3,q4,q5,q6,q7,q8,d,a;
reg [15:0] d=16'b0;//may be error
reg [15:0]a;
always # (posedge p) begin
d<=d+1;
end
DFF dff0(q1,d,p);
DFF dff1(q2,q1,p);
DFF dff2(q3,q2,p);
DFF dff3(q4,q3,p);
DFF dff4(q5,q4,p);
DFF dff5(q6,q5,p);
DFF dff6(q7,q6,p);
DFF dff7(q8,q7,p);
always # ( posedge c )begin
a = ( q1 + q2 + q3 + q4 + q5 + q6 + q7 + q8 )/8;
end
endmodule
module DFF(q,d,clk);
input [15:0]d;
input clk;
output [15:0]q;
reg [15:0]q;
always # (posedge clk)begin
q <=d;
end
endmodule
Here I am counting the high of pulse p and showing the value in 16 bit d.
And whenever another input c goes from 0 to 1 I am showing the average of last 8 values of d.
Problem:Here everything is working fine but the average value showing deviation of 1 and program is stimulating but not synthesizing .
Depending on which synthesis tool you are using, you may not use a variable initialization. You may need to use a reset signal. You can even make it synchronous with
always # (posedge p) begin
d<=reset ? 0 :d+1;
end
Related
the data is input in the first posedge clock but the output should present after 2 clock cycles.
i've tried using #delay but not quite getting it.
clk=0;
forever #10 clk = ~clk;
always # (posedge clk) begin //synchronous rst
#60 q<=d;
end
One way to solve your problem would be to have 2 flip-flops.
reg q1, q2;
always #(posedge clk) begin
q1 <= d;
q2 <= q1;
end
Now, q2 will follow the input with a 2 clock-cycle latency, which is what you wanted.
I am working with a verilog module (shown below) has two always blocks. Won't there be some sort of race condition since one block sets a register and the other uses the register. What kind of issues would this cause?
Thanks,
Stephen
module XYZ
(
input wire CLK,
input wire Reset,
input wire nReset,
input wire [15:0] X,
input wire [15:0] A,
input wire T,
input wire B,
output reg M
);
assign C = X > A;
reg P;
reg N;
always #(posedge CLK, negedge nReset)
begin
if (~nReset)
begin
P <= 1;
N <= 1;
end else begin
if (Reset)
begin
P <= 1;
N <= 1;
end else begin
P <= T? 1: ((C & ~M)? 0: P);
N <= B? 1: ((M & ~C)? 0: N);
end
end
end
always #(posedge CLK, negedge nReset)
begin
if (~nReset)
begin
M <= 0;
end else begin
if (Reset)
begin
M <= 0;
end else begin
M <= M? ~(N & ~C): (P & C);
end
end
end
endmodule
No, there is no race condition. Verilog is an event-driven simulator. Posedge (unless there is a glitch in the clock or reset) is usually executed once per the simulation tick. If you use non-blocking assignments correctly (and it looks like you did), every always block triggered by an edge will use old versions of the input variable values, the values which existed before the clock edge.
Here is a simplified example:
always #(posedge clk)
r <= in;
always #(posedge clk)
out <= r;
What happens in this situation is the following:
r will be assigned the value of in later at the simulation tick, after the always blocks have been evaluated (see the nba scheduling region).
since r has not been yet really changed, the out will be scheduled to be assigned the value of r with the value before the edge.
If r was 0 before the edge and in was 1, at the end of the simulation r will become 1 and out will become 0.
This mimics behavior for real flops in hardware.
In your case it might look as a loop dependency. In reality it it none. For the same reason as above the M value will be the one from before the the posedge and will not cause any race. Flops cannot be involved in the combinational loops due to their properties logical properties.
I completely Agree with the above answer and i would suggest some more to the above answer, when i started learning Verilog i too got the same doubt and these lines from a ref. book clarified my doubts. I am coping the statement here and
for further doubts u can comment here or u can see the
Ref. book page number 135
Book name :Verilog HDL: A Guide to Digital Design and Synthesis,
Second Edition By Samir Palnitkar
nonblocking statements used in Example 2 eliminate the race condition.
At the positive edge of clock, the values of all right-hand-side
variables are "read," and the right-hand-side expressions are
evaluated and stored in temporary variables. During the write
operation, the values stored in the temporary variables are assigned
to the left-handside variables. Separating the read and write
operations ensures that the values of registers a and b are swapped
correctly, regardless of the order in which the write operations are
performed.
On the downside, nonblocking assignments can potentially cause a
degradation in the simulator performance and increase in memory usage.
//Example 2: Two concurrent always blocks with nonblocking
//statements
always #(posedge clock)
a <= b;
always #(posedge clock)
b <= a;
And u can use this type of coding style not compulsory but for the ease of debugging and to fasten simulation u can reduce the usage of begin-end blocks where ever possible
module XYZ
(
input wire CLK,
input wire Reset,
input wire nReset,
input wire [15:0] X,
input wire [15:0] A,
input wire T,
input wire B,
output reg M
);
reg P,N;
always #(posedge CLK, negedge nReset)
if (~nReset)begin
P <= #10 1;
N <= #10 1;
end else if (Reset) begin
P <= #10 1;
N <= #10 1;
end else begin
P <= #10 T ? 1 : ((C & ~M) ? 0: P);
N <= #10 B ? 1 : ((M & ~C) ? 0: N);
end
always #(posedge CLK, negedge nReset)
if (~nReset) M <= #10 0 ;
else if ( Reset) M <= #10 0 ;
else M <= #10 M ? ~(N & ~C): (P & C);
assign C = X > A;
endmodule
I want to write a behavioral verilog code for a FF with the following characteristics as shown in the picture.
module DFF ( D, CK, RN, Q );
input D, CK, RN;
output reg Q;
always # (posedge CK)
begin
if ( RN==1'b0 )
Q <= RN ;
if ( RN==1'b1 )
Q <= D ;
if RN
I DONT KNOW WHAT TO WRITE HERE
end
);
endmodule
From your function table, RN seems to be treated as an asynchronous input.
In that case, negedge RN should also be added to the sensitivity list.
The remaining is the same as #Serge's answer.
always #(posedge CK or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
There is nothing to write there. It is easier, like the following:
always #(posedge clk)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
The only way the Q can be changed is at the posedge of clk. So, your last row in the table is fulfilled here.
The rest is obvious, and you almost got it in your code.
You can use RN as rhs in your code, but it limits flexibility and usually constants are used there.
I am trying to create a 4 bit counter using D flip flops in Verilog. I am following this diagram http://i.imgur.com/VR5593a.png. I got the code for the individual D flip flop. The problem I am having is with D0 in the first clock cycle. I am guessing I have to assume Q0 to be 1 and Q1, Q2, Q3 to be 0 at first. I am not sure how to pass the initial value for D0 only once in the code.
module DFlipFlop(CLK, D, Q);
input CLK, D;
output Q;
reg Q;
always #(posedge CLK) begin
Q <= D;
end
endmodule
module RippleMod(CLK, q0, q1, q2, q3);
input CLK;
output q0, q1, q2, q3;
DFlipFlop d1 (CLK,q3,q0);//not sure about q3 there, think I will get X if i do this.
DFlipFlop d2 (CLK,q0,q1);
DFlipFlop d3 (CLK,q1,q2);
DFlipFlop d4 (CLK,q2,q4);
endmodule
Using a reset signal will help you. So you just need to reset Q3 to 1 and the rest of the signals to 0.
You need to do something to set the initial state.
For simulation you can generally use "initial" blocks to set the initial state of registers. Some synthesis tools, especially those targeting FPGAs/CPLDs also support setting initial states in this way. Some synthesis tools that do not support initial blocks may support a tool-specific way of setting initial conditions.
The other option is to build a reset line into your flip-flops. The downside of this is of course that you then need something to trigger the reset line, either your testbench in simulation or some kind of hardware in a real implementation.
verilog initializes all 4-state variables to 'x'. so, you would run an 'x' around the loop forever without any real change. You need to provide an input to your case. something like the following (in SV)
module RippleMod(CLK, en, in, q0, q1, q2, q3);
input CLK, en, in;
output q0, q1, q2, q3;
logic d1in;
always_ff #(negedge clk) begin
if (en)
d1in <= in;
else
d1in <= q3;
end
DFlipFlop d1 (CLK,d1in,q0);
DFlipFlop d2 (CLK,q0,q1);
DFlipFlop d3 (CLK,q1,q2);
DFlipFlop d4 (CLK,q2,q4);
endmodule
At first you need to initialise the ring counter otherwise output remains in undefined state xxxx. Try out below code, where ffs are explicitly are initialised using an asynchronous load signal...
module shiftreg;
reg [3:0] in;
output [3:0] q;
reg clk, ld, rst;
dff D0 (q[3], clk, rst, 1'b1, q[0]);
dff D1 (q[0], clk, rst, 1'b0, q[1]);
dff D2 (q[1], clk, rst, 1'b0, q[2]);
dff D3 (q[2], clk, rst, 1'b0, q[3]);
initial clk = 0;
initial forever #5 clk = ~clk;
initial begin
$monitor($time, "ld = %b q = %b", ld, q);
#100 $finish;
end
endmodule
module dff (d, clk, rst, ld, q);
input d, clk, ld, rst;
output reg q;
initial if (ld) q <= 1; else q <=0;
always # (posedge clk)
if (rst == 1)
q <= 0;
else q <=d;
endmodule
Ive been doing verilog HDL in quartus II for 2 month now and have not synthesized any of my codes yet. I am struggling to code a fractional division circuit. Of course theres a lot of problems...
I would like to know how do I concatenate two registers to form a larger register that I can shift to the right where the shifting of the data would occur at every positive edge of the clock pulse... The data in the newly created register has 3 zeros (MSB) followed by 4 data bits from another register called divider.
For example B=[0 0 0]:[1 0 1 0]
I have tried the following
module FRACDIV (divider,clk,B,START,CLR);
input [3:0] divider;
input START, CLR, clk;
output [6:0] B;
reg [6:0] B;
always # (posedge clk)
begin
B = {3'd0, divider};
if (START == 1'b1)
begin
B=B+B<<1;
end
end
endmodule
Any help would be deeply appreciated as I've been trying to figure this out for 5 hours now...
Mr. Morgan,
Thank you for the tips. The non-blocking statement did help. However the code would not shift perhaps because B is always reinitialized at every clock pulse as it is outside the if statement.
With a fresh new day and a fresh mind and owing to your suggestion using the non-blocking statement I tried this...
module FRACDIV(divider,clk,B,START,CLR);
input [3:0] divider;
input START, CLR, clk;
output [6:0] B;
reg [6:0] B;
always # (posedge clk)
begin
if (START) begin
B <= {3'b0, divider};
end
else begin
B <= B <<1;
end
end
endmodule
The if statement loads data into B whenever START is HIGH. When START is LOW, the data shifts at every positive edge of the clock. Is there anyway to make the data in B to start shifting right after loading it with the concatenated data without the if statement?
Just curious and I still do not feel this code is the most efficient.
When implying flip-flops it is recommended to use <= non-blocking assignments.
When declaring outputs you should also be able to delcare it as a reg, unless you are stuck using a strict verilog-95 syntax.
module FRACDIV (
input [3:0] divider,
input START, CLR, clk,
output reg [6:0] B
);
always # (posedge clk) begin
B <= {3'd0, divider};
if (START == 1'b1) begin
B<=B+B<<1; //This will overide the previous statement when using `<=`
end
end
endmodule
This will simulate in the same way that your synthesised code will perform on the FPGA.