I've been using Verilog and SystemVerilog for many years, but I just came across something which seems weird.
I don't know if it's something I just never noticed or if there is something special about this I am missing.
Basically I have a module which has a 16-bit input, to which I connected an 8-bit signal. This seems like no big deal to me, in fact it's one of the things I love about Verilog/SystemVerilog, since unlike VHDL, you are allowed to do things like that.
I would expect the signal connected to the input port of my module to be right-aligned and zero-padded on the left, but instead it is being padded with Zs.
That causes my simulation to not work, because for example I use that signal to initialize a counter after substracting one from it, which leads XXXX.
Is this behaviour expected? Can I change something in my code to get the behaviour I expected?
This behavior seems reasonable. I ran a simulation on several simulators on EDA Playground, and I got a mix of results: some had the MSBs as 0, others had them as z.
The best approach is to explicitly drive the inputs with the value you desire. For example, if you want the MSBs to be 0, use something like:
module tb;
reg [7:0] data;
// ...
dut i1 ({ {8{1'b0}}, data });
endmodule
This creates a 16-bit expression which is connected to the module input port. The expression is a concatenation of an 8-bit constant and the 8-bit data signal.
If there is a size mismatch happening in your design or testbench, there should be a warning (if not an error) raised from your compiler/simulation tool. There is no default behavior defined to pad with 0 or undriven z, therefore it can be 0-padded or unknown depending on your tool, and you are on your own risk. The best practice is to watch carefully if there is such warning/error already reported, and try to resolve it during compilation/elaboration phase, or better to run a linting tool before compilation.
I am having a bit of trouble instantiating a module in verilog. I am using the Altera Quartus platform to develop and simulate the verilog code.
I have followed this example (among several others):
http://www.asic-world.com/verilog/verilog_one_day4.html
I have written a module (maximum) which finds the maximum between two signed inputs.
Another module I am developing is a systolic array for genetic sequence alignment. The details are not important, however when I try to instantiate a maximum module I get an error.
This is my code so far:
module maximum (a, b, out);
input signed [15:0] a;
input signed [15:0] b;
output reg signed [15:0] out;
always #* begin
if (a>b)
assign out = a;
else
assign out = b;
end
endmodule
and I instantiate in another module systolic_PE (all of this is in the same file seqalign.v)
maximum m0(.a(tempB), .b(diag), .out(tempA));
And I get the error :
'Verilog HDL syntax error at seqalign.v(139) near text "m0"; expecting
"<=" or "="'
I checked everything I have done so far, and I cant seem to see anything I have missed out on.. could anyone be kind enough to guide me?
Also on a side note:
Instantiation of a module in verilog
I was trying to instantiate my module in a if statement, so I tried outside of the if statement in a always #(posedge clk) block, and I get the error
HDL syntax error at seqalign.v(88) near text "("; expecting ";"
Looking over the code you posted in your comment, the issue is from instantiating your module inside your always #(posedge clk) block on line 70. You never instantiate modules inside of procedural blocks (always, initial, etc).
As Verilog is a Hardware Descriptive Language, you have to be in the mindset of designing hardware when writing your code. Module instantiation is like soldering a chip onto a PCB, at design time you either do it, or you dont, and that component stays there for all time. You dont say, well, I want this chip here some of the time, but take it off the PCB when the system gets into these states. In your code, you conditionally instantiate your module if state is 3. However, state changes over time. So that is akin to saying, when the register containing state reads 3, place down this chip into the system, otherwise, it doesnt exist and take it out. On a code level, think of instantiated modules as their own procedural blocks, just as you dont put always inside of other always, dont put modules in always blocks (of course, module definitions/declarations can have always blocks inside them).
Modules are persistent and compile time constant, so you can use generates to conditionally instantiate modules at compile time (ie, decide whether or not to include the module in the design when building the system). But in your code, you are conditionally instantiating at simulation time, which is not allowed as described above.
You can do one of two things to solve your problem. One would be to move your task from your submodule maximum into the systolic_PE module and use it to get the maximum of your variables tby calling it (line 123 would become something like tempA <= convert(.a(0), .b(diag+match)); with a and b added as inputs to your task). Or, instantiate the module outside the always block, but youll need to change your task to be a procedural block like you have in the actual post.
Apology the title does not explain the question very well, I'll explain it in detail down below.
I'm new to verilog and got painfully stuck with my first lab assignment. One task is to make a 4*4 carry save multiplier, which is made of two types of multipliers, which are in turn made of full adders and AND gates, full adders are made of half adders. I built from the simplest half adders all the way up to the carry save multiplier.
two types of multipliers: http://i129.photobucket.com/albums/p205/Jack_Tianyu_Yang/Capture1_zpsf34b724c.png
hand-drawing of the carry save multiplier
http://i129.photobucket.com/albums/p205/Jack_Tianyu_Yang/photo_zps905f2c13.jpg
The code for the carry save multiplier is here. I instantiated the two types of multipliers and use a lot of internal wires for connections. (I admit it's pretty naive but this is the best i can do for the time being, I'll keep practicing and get better at it.) My QUESTION is this: refer to the "hand-drawing" ,the most left module on the top row, you can see there are two ports---q0_out and q1_out, that are outputs of this multiplier module BUT not part of the outputs in the main output list. Actually, q0_out,q1_out,q2_out,q3_out and m0_out,m1_out,m2_out,m3_out are all not in the output list. They are actually the same value of q0 to q3 and m0 to m3,respectively. (This can be verified by the first image)
When I synthesized the code I pasted below, Xilinx ISE gave me a bunch of same warnings saying for example :"Assignment to q3_out ignored, since the identifier is never used".
When I ask the TA, he said I should "treat the 4*4 carry save multiplier as a black box and the only inputs are m3m2m1m0, q3q2q1q0 and the only output is p7p6p5p4p3p2p1. Outputs like q3_out are 'internal' and should not be presented in the final output list". I don't how to deal with this situation. As you can see, I simply assign q3 to q3_out because q3_out is the same value propagated all the way from q3.
Please feel free to comment on my codes (what to improve, what's a bad coding style) and ask me for more elaboration of the question, also, if possible, please please share some ideas of how to solve this problem. Thank you all in advance.
`timescale 1ns / 1ps
module multiplier44_OMG(
input m0,m1,m2,m3,q0,q1,q2,q3,
output p0,p1,p2,p3,p4,p5,p6,p7
);
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18,w19,w20;
wire w21,w22,w23,w24,w25,w26,w27,w28,w29,w30,w31,w32,w33,w34,w35,w36,w37; //Internal wires
wire cin0,cin1,cin2,mk1_mul2_3; //These inputs are feeding into the carry save multiplier and are all zeroes.
wire q0_out,q1_out,q2_out,q3_out,m0_out,m1_out,m2_out,m3_out;
assign cin0=1'b0;
assign cin1=1'b0;
assign cin2=1'b0;
assign mk1_mul2_3=1'b0;// Inputs are assigned to zero.
assign q0_out=q0;
assign q1_out=q1;
assign q2_out=q2;
assign q3_out=q3;
assign m0_out=m0;
assign m1_out=m1;
assign m2_out=m2;
assign m3_out=m3;//THIS IS THE PART I DON'T KNOW HOW TO DEAL WITH
and (p0,m0,q0);
multiplier2 mul2_0(m1,m0,q0,q1,cin0,w1,w2,w3,w4,p1);
multiplier2 mul2_1(m2,m1,w1,w2,w3,w5,w6,w7,w8,w9);
multiplier2 mul2_2(m3,m2,w5,w6,w7,w10,w11,w12,w13,w14);
multiplier2 mul2_3(mk1_mul2_3,m3,w10,w11,w12,q0_out,q1_out,w15,w16,w17);
multiplier mul_0(w9,w4,q2,cin1,w18,w19,w20,p2);
multiplier mul_1(w14,w8,w18,w19,w21,w22,w23,w24);
multiplier mul_2(w17,w13,w21,w22,w25,w26,w27,w28);
multiplier mul_3(w15,w16,w25,w26,q2_out,w29,w30,w31);
multiplier mul_4(w24,w20,q3,cin2,w32,w33,m0_out,p3);
multiplier mul_5(w28,w23,w32,w33,w34,w35,m1_out,p4);
multiplier mul_6(w31,w27,w34,w35,w36,w37,m2_out,p5);
multiplier mul_7(w29,w30,w36,w37,q3_out,p7,m3_out,p6);
endmodule
It's does not feel any good staring at the code alone in the lab on a friday night.(Plus it's Spring festival.) I know my question is quite elementary, but even though I need help, GREAT help from the GREAT netizens.
A warning is just a warning, it's not an error. If you have a signal that is generated that has no load, then the synthesizer warns you, but there's nothing really there to 'fix'.
Also, since q3_out is output from mul_7, you shouldn't be driving it with a separate assign statement. Each wire should only have one driver.
I just want to use some if else statement in verilog.
So I have to use always block.
integer count,index;
reg a=0;
always#(a) begin
a=1;
for(count=0;count<7;count=count+1) begin
index=4*count;
if((significand[index]==1'b0)&&(significand[index+1]==1'b0)&&
(significand[index+2]==1'b0) &&(significand[index+3]==1'b0))
lzero=lzero+1;
end
end
This code does make some sense now. I was able to get the correct simulation result, but I failed to get the correct synthesis on the board. Please help
This is a very typical problem with people who know how to program in C or C++ but forget that Verilog and VHDL are not the same as those.
EVERY signal line of Verilog code inside the ALWAYS block are 'executed' at the same time. The same goes with the combinatorial logic outside of the ALWAYS block.
In your code, both the
assign a=1'b1;
assign a=1'b0;
Will happen at the same time, no matter what.
The only way to change that is to put the last line inside your always block,after the end statement of the for loop.
One page that will give you some help on understanding the difference between C and Verilog is the page:EE-Times: The C Programmers Guide to Verilog
Neither assign 1'b1; nor assign 1'b0; are valid assignments. If you want to constantly drive some net with 1'b1, then you have to write something like assign myvar = 1'b1;.
Also, if your intent was to actually assign to a, then always block doesn't make sense since a is the only thing in its sensitivity list meaning that that block must be executed whenever a changes its value. Since a will essentially never change its value, that block should never be executed.
It is hard to help you out unless you provide a minimal working example demonstrating your problem. The only thing that I can recommend is to use ternary operator in assign right hand side statement. That way you can model a behavioural logic without using always block. For example:
assign a = (b == 1'b1 ? c : 1'b0);
Hope it helps.
UPDATE:
Your second code example is neither complete nor legal as well. You cannot have two combinatorial assignments for the same net.
However, a sensitivity list in always block is now a star, which is Verilog 2001 notation to include all right hand side operands into a sensitivity list automatically. In your case, the block will get executed every time significand or lzero changes.