How do I run the verilog code on a testbench? - verilog

Question

I wrote the code for a ripple carry adder. Testbench is also available. How do I run this test bench on my Verilog code? I don't have a simulator. I am using the iverilog compiler.
ripple_carry_adder.v
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule
module full_adder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire t1,t2;
half_adder h(a,b,t1,t2);
assign cout=t1&cin;
assign sum=t1^cin;
assign cout=t2|cout;
endmodule // full_adder
module ripple_carry_adder(input1,input2,answer);
input [31:0] input1,input2;
output [31:0] answer;
wire [31:0] carry;
full_adder f(input1[0],input2[0],1'b0,answer[0],carry[0]);
genvar i;
generate
for(i=1;i<=31;i=i+1)
begin : my_mabel
full_adder f(input1[i],input2[i],carry[i-1],answer[i],carry[i]);
end
endgenerate
endmodule
testbench
module test;
reg [31:0] input1,input2, expected;
wire [31:0] actual;
integer seed;
ripple_carry_adder dut(input1,input2,actual);
initial begin
seed = 0;
repeat(10) begin
input1 = $random(seed);
input2 = $random(seed);
expected = input1 + input2;
#1;
if(actual!=expected) $display("ERROR: %0d+%0d was %0d expected %0d",
input1,input2,actual, expected);
#9;
end
end
endmodule

Answer 1

Use:
$ iverilog -o ripple ripple_carry_adder.v ripple_carry_adder_tb.v
$ vvp ripple
to compile and run your code in terminal. You might add a $monitor to your testbench to be able to print some more results than just errors.
There is also a companion program called GTKWave that allows you to plot waveforms.