writing a ripple carry adder in verilog - verilog

Question

I'm attempting to write a ripple carry adder in verilog.
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule
module full_adder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire t1,t2;
half_adder h(a,b,t1,t2);
assign cout=t1&cin;
assign sum=t1^cin;
assign cout=t2|cout;
endmodule // full_adder
module ripple_carry_adder(input1,input2,answer);
input [31:0] input1,input2;
output [31:0] answer;
integer carry,t;
genvar i;
initial begin
assign carry=1'b0;
end
for(i=0;i<=31;i=i+1)
begin
full_adder f(input1[i],input2[i],carry,answer[i],t);
assign carry=t;
end
endmodule
however when i compile using the iverilog simulator, the following error log shows up(repetitive errors removed) :
ripple_carry_adder.v:28: warning: Couldn't build unique name for unnamed generate block - using internal name $gen1
ripple_carry_adder.v:30: warning: Port 3 (cin) of full_adder expects 1 bits, got 32.
ripple_carry_adder.v:30: : Pruning (signed) 31 high bits of the expression.
ripple_carry_adder.v:30: error: reg t; cannot be driven by primitives or continuous assignment.
ripple_carry_adder.v:30: error: Output port expression must support continuous assignment.
ripple_carry_adder.v:30: : Port cout of full_adder is connected to t
ripple_carry_adder.v:31: error: reg carry; cannot be driven by primitives or continuous assignment.
ripple_carry_adder.v:28: warning: Couldn't build unique name for unnamed generate block - using internal name $gen1
ripple_carry_adder.v:30: warning: Port 3 (cin) of full_adder expects 1 bits, got 32.
ripple_carry_adder.v:30: : Pruning (signed) 31 high bits of the expression.
ripple_carry_adder.v:30: error: reg t; cannot be driven by primitives or continuous assignment.
ripple_carry_adder.v:30: error: Output port expression must support continuous assignment.
ripple_carry_adder.v:30: : Port cout of full_adder is connected to t
ripple_carry_adder.v:31: error: reg carry; cannot be driven by primitives or continuous assignment.
Where am I going wrong?
EDIT: Using the generate statement now.Still have doubt about the type of carry.
module ripple_carry_adder(input1,input2,answer);
input [31:0] input1,input2;
output [31:0] answer;
wire carry;
wire t;
initial begin
carry=1'b0;
end
genvar i;
generate for(i=0;i<=31;i=i+1)
begin
full_adder f(input1[i],input2[i],carry,answer[i],t);
carry=t;
end endgenerate
endmodule

Answer 1

You should get rid of the initial block. You can drop t. Then using an generate block:
wire [31:0] carry;
genvar i;
full_adder f(input1[0],input2[0],1'b0,answer[0],carry[0]);
generate // optional in IEEE std 1364-2005 and IEEE std 1800
for(i=1;i<=31;i=i+1)
begin
full_adder f(input1[i],input2[i],carry[i-1],answer[i],carry[i]);
//assign carry=t;
end
endgenerate
endmodule
Alternatively, something that worked with the old 1364-1995 style:
full_adder f[31:0](input1[31:0],input2[31:0],{carry[30:0],1'b0},answer[31:0],carry[31:0]);

Answer 2

assign statements are not to be used inside of statement blocks. Anytime you have a begin/end block, the left-hand side of the statement gets set without using the assign keyword. e.g.:
initial begin
carry = 1'b0
end
You cannot instantiate modules inside a procedural block or for-loop (e.g. full_adder), you need to use a generate statement instead. You declared a genvar, so I think you meant to do this, but you don't seem to have the generate statement.
You cannot drive a reg/integer type from the output of a module, reg/integers can only be driven from a procedural block. Change type t from an integer to a wire[31:0] instead.