I need to implement a 32 bit adder subtractor ALU for a class assignment. I have a 1-bit adder subtractor that works fine and the operation is made with the help of a select statement (code for all is given below). Anyway, the problem I am facing is that I am unable to figure out how to use the carry/borrow out of one module to the subsequent module.
module add_sub(select, i0, i1, cin, out, cout
);
input i0, i1, select, cin;
output out, cout;
wire y0, y1, y2, y3, y4, y5, y6;
wire z0, z1, z2, z3, z4;
//diff = i0 xor i1 xor cin
//borrow = cin. ~(i1 xor i2) or ~x.y
xor (y0, i1, cin);
xor (y1, i0, y0); //y1=diff or sum as only carry and borrow vary between adder and subtractor circuits
xor (y2, i1, i0);
and (y3, cin, ~y2);
and (y4, ~i0, i1);
or (y6, y5, y4); //y6 = borrow
and (z0, i0, i1);
xor (z1, i0, i1);
and (z2, cin, z1);
or (z3, z0, z2); //z3= carry out for sum
//conditional operator for assigning sum or difference. if select = 0, we add, else subtract
assign out = y1;
assign cout = select ? y6 : z3;
endmodule
This module is instantiated in a loop in the alu module that is given below...
module alu(sel, num1, num2, alu_cin, alu_out, alu_c
);
parameter N = 32;
input sel; //select line for add or sub
input [N-1:0] num1; //two inputs
input [N-1:0] num2;
input alu_cin;
output [N-1:0] alu_out; //32 bit output
output alu_c; // becomes final carry or borrow accordingly
genvar i;
generate for (i=0; i<=N-1; i=i+1)
begin: alu_loop
if (i == 0)
add_sub as_i (sel, num1[i], num2[i], alu_cin, alu_out[i], alu_c);
else
add_sub as_i (sel, num1[i], num2[i], alu_loop[i-1].as_i.cout[i-1], alu_out[i], alu_c);
end
endgenerate
endmodule
In the test bench for the alu, I gave appropriate 32 bit values and the select value as I need. The problem comes with
add_sub as_i (sel, num1[i], num2[i], alu_loop[i-1].as_i.cout[i-1], alu_out[i], alu_c);
It says "Indexing cannot be applied to a scalar." as I am trying to simulate it. Syntax check is completed perfectly.
I need access to cout from the one-bit module to pass it on as cin to the next one. The alu_c can be overwritten as only the last one bit is needed.
Any help would be appreciated. Thanks in advance. :) All this is done on Xilinx ISE through Verilog modules.
It is syntactically correct but you are using a bit-select on a single bit value, which is a semantic error.
add_sub as_i (
sel,num1[i],num2[i],alu_loop[i-1].as_i.cout[i-1],alu_out[i],alu_c);
^^^^
Declared as scalar output in add_sub
output out, cout;
While Verilog allows referencing a port using the dot notation(hierarchical referencing), it's not a good practice outside of testbenches. You should declare a wire for that connectivity instead.
for (i=0; i<=N-1; i=i+1)
begin: alu_loop
wire cout; // Visible as alu_loop[N].cout
end
Related
I have to make a 64 Bit ALU that takes in A and B 64-bit inputs, a carry_in input and outputs a 64bit result along with a 1-bit carry_out. There is also a 5 bit function-select FS. Where FS[0] controls whether B is inverted or not (using a 2to1 mux.) F[1] does the same for the A. And FS[4:2] determines which operation (Adding, subtracting, logical operations, etc) using an 8to1 Mux. Below is the code for the ALU and Testbench.
I'm pretty sure my testbench is good and so is all the separate components for the ALU. I'm not too confident about my top-level where I instantiate and connect all the inputs/outputs. What is causing the high impedance in the waveform?
module ALU(A, B, FS, cin, cout, result);
input [63:0] A, B;
input [4:0] FS;
input cin;
output cout;
output [63:0] result;
eight_one_mux u7 (firstoutA & secoutB, firstoutA | secoutB, sum, firstoutA ^ secoutB,
left, right, 1'b0, 1'b0, FS[4:2], result);
adder u6 (firstoutA, secoutB, cin, sum, cout);
firstmux u1 (A, !A, FS[1], firstoutA);
secmux u2 (B, !B, FS[0], secoutB);
Alu_shifter u5 (A, left, right);
endmodule
//--------------------------------------------------------------------------------//
//These are the two muxes to split into input and inverted input A,B
module firstmux(a, nota, firstS, firstoutA);
input [63:0] a, nota;
input firstS;
output reg [63:0] firstoutA;
always #(a or nota or firstS)
begin
case(firstS)
0 : firstoutA = a;
1 : firstoutA = nota;
default : firstoutA = 1'bx;
endcase
end
endmodule
//<><><><><><><>//
module secmux(b, notb, secS, secoutB);
input [63:0] b, notb;
input secS;
output reg [63:0] secoutB;
always #(b or notb or secS)
begin
case(secS)
0 : secoutB = b;
1 : secoutB = notb;
default : secoutB = 1'bx;
endcase
end
endmodule
//--------------------------------------------------------------------------------//
//This is the Shifter Blocks
module Alu_shifter (shiftA, right, left); //This shifter block shifts the A input once right or left
input [63:0] shiftA;
output [63:0] right;
output [63:0] left;
shift_right w1 ( //instantiate right shifter block
.a_R(shiftA),
.R(right)
);
shift_left w2 ( //instantiate left shifter block
.a_L(shiftA),
.L(left)
);
endmodule
////////><><><><><><><><><><><><><><><///////
module shift_right (a_R, R); // right shifter block
input [63:0] a_R;
output [63:0] R;
assign R = a_R >> 1; //shift A right once (shift in a 0)
endmodule
module shift_left (a_L, L); //left shifter block
input [63:0] a_L;
output [63:0] L;
assign L = a_L << 1; //shift A left once (shift in a 0)
endmodule
//End shifter blocks (3 total modules)
//----------------------------------------------------//////////////////////
//This is the Adder that Adds A, B and cin
module adder(addA, addB, nic, sum, cout);
input [63:0] addA, addB;
input nic;
output [63:0] sum;
output cout;
assign {cout, sum} = addA + addB + nic;
endmodule
//----------------------------------------------------//////////////////////
//This is the 8to1 Mux that decides which operation is put forward
module eight_one_mux(D0, D1, D2, D3, D4, D5, D6, D7, S, out);
input [63:0] D0, D1, D2, D3, D4, D5, D6, D7;
input [2:0] S;
output reg [63:0] out;
always #(D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7 or S)
begin
case(S)
0 : out = D0; //And
1 : out = D1; //Or
2 : out = D2; //Adder
3 : out = D3; //xor
4 : out = D4; //lefter
5 : out = D5; //righter
6 : out = D6; //GND
7 : out = D7; //GND
default : out = 1'bx;
endcase
end
endmodule
////////////-------------------------------////////////////////////////////
module ALU_tb();
reg [63:0] A, B;
reg [4:0] FS;
reg cin;
wire cout;
wire [63:0] result;
ALU dut (
.A(A),
.B(B),
.FS(FS),
.cin(cin),
.cout(cout),
.result(result)
);
initial begin
A = 8'b11001100;
B = 8'b11001101;
FS = 5'b01101;
cin = 1;
end
always
#5 cin <= ~cin;
always begin
#5
A <= A + 1;
B <= B + 2;
#5;
end
initial begin
#100 $finish;
end
endmodule
```
Unexpected high impedance (z) values are typically the result of undriven signals, and that is the problem with your code.
adder u6 (firstoutA, secoutB, cin, sum, cout);
In the line above, you connect the 1-bit signal firstoutA to the 64-bit addA input port. This connects firstoutA to addA[0], leaving the other 63 bits undriven. Thus, addA[63:1] are all z.
firstoutA is a 1-bit signal because you did not explicitly declare it. Also, undeclared signals are assumed to be of type wire, which default to z.
It is good practice to declare all signals.
To find all undeclared signals, add this to the top of your code:
`default_nettype none
You should get compile errors like:
Error-[IND] Identifier not declared
Identifier 'firstoutA' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
Error-[IND] Identifier not declared
Identifier 'secoutB' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
First you need to define signals (wire) for connections between modules. For example, you have left and right as outputs of Alu_shifter module and they are connected to firstmux and secmux modules; however, they are not defined in your top module. You should add following signal definitions to your topmodule:
wire [63:0] left,right;
wire [63:0] firstoutA;
wire [63:0] secoutB;
wire [63:0] sum;
Also, eight_one_mux module takes eight 64-bit inputs. However, you set the last two of them as 1'b0. You should change them to 64'b0 as below.
eight_one_mux u7 (firstoutA & secoutB, firstoutA | secoutB, sum, firstoutA ^ secoutB,
left, right, 64'b0, 64'b0, FS[4:2], result);
Finally, !A does not invert all bits of A (same for B). It applies a reduction operation and generates a 1-bit signal (and firstmux module expects a 64-bit signal in its second input port).
My desired functionality will be to add A, B, and cin (where A and B are 64 bits, and cin is one bit). So the actual sum (the actual result) can either be 64 bits or even 65 bits, right? So I want the output "sum" to be 64 bits, and then the carryout output "cout" would hold the most significant bit of the result. Tried doing this by an assign statement, but I guess that's not how you do it as it gives an error. Any other way?
module addsub(A, B, cin, sum, cout);
input [63:0] A, B;
input cin;
output reg [63:0] sum;
output cout;
reg [64:0] actualsum; // the actual result of the addition, which I want to then "split" into cout & sum
always #(A or B or cin) begin
actualsum = A + B + cin;
sum <= actualsum[63:0];
cout <= actualsum[64];
end
endmodule
The compile error I got was due to a procedural assignment to cout (inside an always block). To fix that, you would declare cout as a reg.
Good coding practices recommend that you use blocking assignments (=) instead of nonblocking assignments (<=) for combinational logic.
A much simpler and more conventional way to code this is:
module addsub (
input [63:0] A, B,
input cin,
output [63:0] sum,
output cout
);
assign {cout, sum} = A + B + cin;
endmodule
I'm trying to us a 1 bit full subtractor by a 4 bit module as so - I'm a little stuck on where to go next, I'm not sure what's happening under the hood - I thought maybe I could us fullsub in a loop of sub4 and iterate over each of the bits and update the in vs out, but I'm not sure how to do that.
module fullSub(x, y, b_in, diff, b_out);
input x, y, b_in;
output diff, b_out;
assign diff=(x^y)^b_in;
assign b_out = (~(x^y)&b_in) | ((~x)&y);
endmodule
module sub4(x, y, b_in, diff, b_out);
input [3:0] x, y;
input b_in;
output [3:0] diff;
output b_out;
fullSub init[3:0](x, y, b_in, diff, b_out);
assign b_in = b_out;
endmodule
I used the following and it worked well - thanks.
wire [3:0] borrow
genvar i;
generate
for(i=3; i>=0; i=i-1)
begin: description
if(i===0)
fullSub s(x[i], y[i], b_in, diff[i], borrow[i]);
else
fullSub s(x[i], y[i], borrow[i-1], diff[i], borrow[i]);
end
assign b_out = borrow[3];
endgenerate
I have the following code for a 2 bit multiplier:
module Multiplier (a0, a1, b0, b1, c[3:0]);
output [3:0]c;
input a0, a1, b0, b1;
wire a0b1, a1b0, ha0c, a1b1;
and (c[0], a0, b0);
and (a0b1, a0, b1);
and (a1b0, a1, b0);
HalfAdder ha0 (a1b0, a0b1, c[1], ha0c);
and (a1b1, a1, b1);
HalfAdder ha1 (ha0c, a1b1, c[2], c[3]);
endmodule
I want to be able to expand this to more than 2 bits though (32 bits). The structure of my code poses a challenge for this though. First off I would have to have 68 parameters for the module. Also I would have to manually create 64 wires (duplicates of wire a0b1, a1b0, ha0c, a1b1). Finally I would need to manually write out a bunch of logic gates and HalfAdder modules to connect all the logic. Because of this I am wondering if there is a way that I can refactor my code to be able to instantiate a binary multiplier of n (a passed parameter) size.
You need to parameterize and use a generate block. (And it is much better to use a synchronous circuit then an asynchronous circuit).
Here is an incomplete example, you can fill in the necessary logic :
module Multiplier (a, b, c, clk);
parameter WIDTH = 64;
output [2*WIDTH:0]c;
input [WIDTH-1:0]a;
input [WIDTH-1:0]b;
input clk;
genvar i;
generate for (i = 0; i < WIDTH; i <= i + 1)
begin : shifts
// shift a 1-bit for each i and 'logical and' it with b
reg [WIDTH + i :0]carry;
wire [WIDTH + i -1:0]shifted = {a,i{0}} & b[i];
// sum the result of shift and 'logical and'
always # (posedge clk)
begin
carry <= shifted + shifts[i-1].carry ;
end
end
assign c = shifts[WIDTH].carry;
endgenerate
endmodule
I am working on a ripple carry adder using structural verilog, which is supposed to take in two random inputs and calculate accordingly.
The general rca I created calculated correctly, but for some reason I get weird outputs when I add a for loop and use the $random to generate.
Could someone kindly explain where I'm going wrong? Below is my code:
module full_adder(x,y,z,v,cout);
parameter delay = 1;
input x,y,z; //input a, b and c
output v,cout; //sum and carry out
xor #delay x1(w1,x,y);
xor #delay x2(v,w1,z);
and #delay a1(w2,z,y);
and #delay a2(w3,z,x);
and #delay a3(w4,x,y);
or #delay o1(cout, w2,w3,w4);
endmodule
module four_bit_adder(a,b,s,cout,cin);//four_bit_adder
input [15:0] a,b; //input a, b
input cin; //carry in
output [15:0] s; //output s
output cout; //carry out
wire [15:0] c;
full_adder fa1(a[0],b[0],cin,s[0],c0);
full_adder fa2(a[1],b[1],c0,s[1],c1);
.
.
.
full_adder fa16(a[15],b[15],c14,s[15],cout);
endmodule
module testAdder(a,b,s,cout,cin);
input [15:0] s;
input cout;
output [15:0] a,b;
output cin;
reg [15:0] a,b;
reg cin;
integer i;
integer seed1=4;
integer seed2=5;
initial begin
for(i=0; i<5000; i=i+1) begin
a = $random(seed1);
b = $random(seed2);
$monitor("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
$display("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
end
end
endmodule
Here are two lines from the output that I get:
a=38893, b=58591, cin=x, s= z, cout=z
a=55136, b=58098, cin=x, s= z, cout=z
This is a combinational circuit, so the output changes instantaneously as the input changes. But, here you are apply all the inputs at same timestamp which should not be done since the full_adder module provides 1-timestamp delay. This may not cause problems in this module, but may cause issues while modelling sequential logic. Add a minimum of #10 delay between inputs.
Also, $monitor executes on each change in the signal list, so no need to use it in for loop. Just initialize $monitor in initial condition.
cin is also not driven from the testbench. Default value of reg is 'x and that of wire is 'z. Here, cin is reg, so the default value is displayed, that is 'x
One more thing, you must instantiate the design in your testbench. And connect respective ports. The outputs from testbench act as inputs to your design and vice-versa. This is just like you instantiate full_adder module in four_bit_adder module in design.
Consider testadder as top level module and instantiate design in it. No need of declaring ports as input and output in this module. Declare the design input ports as reg or wire(example: reg [15:0] a when a is design input port) and output ports as wire (example: wire [15:0] sum when sum is design input port).
Referring to your question:
The general rca I created calculated correctly, but for some reason I get weird outputs when I add a for loop and use the $random to generate.
Instead of using $random, use $urandom_range() to generate random numbers in some range. Using SystemVerilog constraints constructs can also help. Refer this link.
Using $urandom_range shall eliminate use of seed1 and seed2, it shall generate random values with some random machine seed.
Following is the module testadder with some of the changes required:
module testAdder();
wire [15:0] s;
wire cout;
// output [15:0] a,b;
// output cin;
reg [15:0] a,b;
reg cin;
integer i;
integer seed1=4;
integer seed2=5;
// Instantiate design here
four_bit_adder fa(a,b,s,cout,cin);
initial begin
// Monitor here, only single time
$monitor("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
for(i=0; i<5000; i=i+1) begin
// Drive inputs with some delays.
#10;
// URANDOM_RANGE for input generation in a range
a = $urandom_range(0,15);
b = $urandom_range(0,15);
// a = $random(seed1);
// b = $random(seed2);
// Drive cin randomly.
cin = $random;
$display("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
end
end
endmodule
For more information, have a look at sample testbench at this link.