Force pin in Verilog to specific frequency - verilog

Question

I have tried looking for the answer to this, but to no avail. I am getting problems when I re-synthesise my code and I suspect that it is due to clock issues.
I am using a DCM to multiply an external crystal oscillator from 25MHz to 50MHz. However, I think that the tool won't know what frequency the crystal oscillator actually is, since it is an external physical component. My code is below:
//since our crystal oscillator is only 25Mhz, we use a DCM to multiply it by two since the desired is 50Mhz
DCM #(
.CLKFX_DIVIDE (2),
.CLKFX_MULTIPLY (4)
) dcm_master (
.CLKFB (CLK_FB),
.CLKIN (CLK_crystal),
.RST (DcmReset),
.CLK0 (MasterClk0Unbuf),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (MasterClkFxUnBuf),
.CLKFX180 (),
.CLKDV (),
.LOCKED (DcmLocked),
.STATUS (),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE ()
);
//we provide feedback to the DCM's phase input (possibly not neccessary)
BUFG bufg_master_dcm_clk_0 ( .I(MasterClk0Unbuf), .O(CLK_FB) );
BUFG bufg_master_dcm_clk_fx ( .I(MasterClkFxUnBuf), .O(CLK_FX) );
//code taken from xilinx. We toggle using a bufgmux between the onboard and external clock
// BUFGMUX: Global Clock Buffer 2-to-1 MUX
// Spartan-3
// Xilinx HDL Libraries Guide, version 13.2
BUFGMUX BUFGMUX_inst (
.O(CLK), // Clock MUX output
.I0(CLK_FX), // Clock0 input
.I1(CLK_local), // Clock1 input
.S(sw[6]) // Clock select input
);
Will this code in the ucf force the tool to recognize the output of my DCM as 50MHz?
PIN "bufg_master_dcm_clk_fx.O" TNM_NET = CLK50;
TIMESPEC TS_CLKBuf = PERIOD "CLK50" 100 MHz HIGH 50%;
Furthermore, am I using the BUFG's correctly? Xilinx says I should use an IBUFG to connect the external clock into my DCM, and I am getting errors saying my BUFG's can only address half the chip (which I imagine is going to become troublesome).
thanks,
Nathan

Answer 1

I think your clock constraints are off. You should be constraining the input to the DCM -- the DCM knows what to do with the outputs. Here's what I would use:
NET clk_in TNM_NET = tnm_clk_in;
TIMESPEC TS_clk_in = PERIOD tnm_clk_in 40ns;
where clk_in is the crystal (CLK_crystal in your case). Make sure that the crystal is connected to a clock pin on your device.

Answer 2

I would have liked to test this out first. For the Spartan-3 family of FPGAs, using one of the DCMs. This is the template that ISE produces.
Notice that there is a dedicated CLK2X.
Also, based on the user manual: .CLKFB should be driven by a BUFG source.
wire i_FeedBack;
wire o_FeedBack;
BUFG clkFBBuf(
.I(i_FeedBack),
.O(o_FeedBack)
);
DCM #(
[...]
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(2), // Can be any integer from 2 to 32
[..]
) DCM_inst (
.CLK0(i_FeedBack), // 0 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
[...]
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
.CLKFB(o_FeedBack), // DCM clock feedback
.CLKIN(clk), // Clock input (from IBUFG, BUFG or DCM)
[...]
);