I am getting an error when running the following makefile with make -f makefile2 install (apart install the rest is working):
all:myapp
#which compiler
CC = gcc
#Where to install
INSTDIR = /usr/local/bin
#where are include files kept
INCLUDE = .
#Options for development
CFLAGS = -g -Wall -ansi
#Options for release
# CFLAGS = -O -Wall -ansi
myapp: main.o 2.o 3.o
$(CC) -o myapp main.o 2.o 3.o
main.o: main.c a.h
$(CC) -I$(INCLUDE) $(CFLAGS) -c main.c
2.o: 2.c a.h b.h
$(CC) -I$(INCLUDE) $(CFLAGS) -c 2.c
3.o: 3.c b.h c.h
$(CC) -I$(INCLUDE) $(CFLAGS) -c 3.c
clean:
-rm main.o 2.o 3.o
install: myapp
#if [ -d $(INSTDIR) ]; \
then \
cp myapp $(INSTDIR);\
chmod a+x $(INSTDIR)/myapp;\
chmod og-w $(INSTDIR)/myapp;\
echo "Installed in $(INSTDIR)";\
else
echo "Sorry, $(INSTDIR) does not exist";\
fi
I'm getting the following error:
error /bin/sh: 7: Syntax error: end of file unexpected
make: *** [install] Error 2
From what I understand it is a white space/tabulation/non unix character problem in the last lines of the makefile (after install:). But even trying to delete all spaces and replacing with tabulation I didn't manage to run the makefile properly. The code comes directly from a programming book I'm reading and is an example. Any help appreciated!
You're missing a trailing slash on your else under the install rule. It should be:
install: myapp
#if [ -d $(INSTDIR) ]; \
then \
cp myapp $(INSTDIR);\
chmod a+x $(INSTDIR)/myapp;\
chmod og-w $(INSTDIR)/myapp;\
echo "Installed in $(INSTDIR)";\
else\
echo "Sorry, $(INSTDIR) does not exist";\
fi
Related
I am trying to add this package called sane-airscan to my yocto build. My experience with yocto is very basic.I do not know how to write a recipe for this one
This is the MakeFile for the above mentioned one
# USER-SETTABLE VARIABLES
#
# The following variables can be overridden by user (i.e.,
# make install DESTDIR=/tmp/xxx):
#
# Name Default Description
# ---- ------- -----------
# DESTDIR Destination directory for make install
# PREFIX Non-standard: appended to DESTDIR
# CC gcc C compiler
# CPPFLAGS C preprocessor flags
# CFLAGS -O2 -g -W -Wall -Werror C compiler flags
# LDFLAGS Linker flags
# COMPRESS gzip Program to compress man page, or ""
# MANDIR /usr/share/man/ Where to install man page
CC = gcc
COMPRESS = gzip
CFLAGS = -O2 -g -W -Wall -Werror
MANDIR = /usr/share/man/
PKG_CONFIG = /usr/bin/pkg-config
# These variables are not intended to be user-settable
OBJDIR = objs/
BINDIR = /usr/bin
CONFDIR = /etc/sane.d
LIBDIR := $(shell $(PKG_CONFIG) --variable=libdir sane-backends)
BACKEND = libsane-airscan.so.1
DISCOVER = airscan-discover
LIBAIRSCAN = $(OBJDIR)/libairscan.a
MAN_DISCOVER = $(DISCOVER).1
MAN_DISCOVER_TITLE = "SANE Scanner Access Now Easy"
MAN_BACKEND = sane-airscan.5
MAN_BACKEND_TITLE = "AirScan (eSCL) and WSD SANE backend"
DEPENDS := avahi-client avahi-glib libjpeg libsoup-2.4 libxml-2.0
DEPENDS += libpng
# Sources and object files
SRC = $(wildcard airscan-*.c) sane_strstatus.c
OBJ = $(addprefix $(OBJDIR), $(SRC:.c=.o))
# Obtain CFLAGS and LDFLAGS for dependencies
airscan_CFLAGS = $(CFLAGS)
airscan_CFLAGS += -fPIC
airscan_CFLAGS += $(foreach lib, $(DEPENDS), $(shell pkg-config --cflags $(lib)))
airscan_LIBS := $(foreach lib, $(DEPENDS), $(shell pkg-config --libs $(lib))) -lm
airscan_LDFLAGS = $(LDFLAGS)
airscan_LDFLAGS += $(airscan_LIBS)
airscan_LDFLAGS += -Wl,--version-script=airscan.sym
# This magic is a workaround for libsoup bug.
#
# We are linked against libsoup. If SANE backend goes unloaded
# from the memory, all libraries it is linked against also will
# be unloaded (unless main program uses them directly).
#
# Libsoup, unfortunately, doesn't unload correctly, leaving its
# types registered in GLIB. Which sooner or later leads program to
# crash
#
# The workaround is to prevent our backend's shared object from being
# unloaded when not longer in use, and these magical options do it
# by adding NODELETE flag to the resulting ELF shared object
airscan_LDFLAGS += -Wl,-z,nodelete
$(OBJDIR)%.o: %.c Makefile airscan.h
mkdir -p $(OBJDIR)
$(CC) -c -o $# $< $(CPPFLAGS) $(airscan_CFLAGS)
.PHONY: all clean install man
all: tags $(BACKEND) $(DISCOVER) test test-decode
tags: $(SRC) airscan.h test.c test-decode.c
-ctags -R .
$(BACKEND): $(OBJDIR)airscan.o $(LIBAIRSCAN) airscan.sym
$(CC) -o $(BACKEND) -shared $(OBJDIR)/airscan.o $(LIBAIRSCAN) $(airscan_LDFLAGS)
$(DISCOVER): $(OBJDIR)discover.o $(LIBAIRSCAN)
$(CC) -o $(DISCOVER) discover.c $(CPPFLAGS) $(airscan_CFLAGS) $(LIBAIRSCAN) $(airscan_LIBS) -fPIE
$(LIBAIRSCAN): $(OBJ) Makefile
ar cru $(LIBAIRSCAN) $(OBJ)
install: all
mkdir -p $(DESTDIR)$(PREFIX)$(BINDIR)
mkdir -p $(DESTDIR)$(PREFIX)$(CONFDIR)
mkdir -p $(DESTDIR)$(PREFIX)$(CONFDIR)/dll.d
install -s -D -t $(DESTDIR)$(PREFIX)$(BINDIR) $(DISCOVER)
cp -n airscan.conf $(DESTDIR)$(PREFIX)$(CONFDIR)
cp -n dll.conf $(DESTDIR)$(PREFIX)$(CONFDIR)/dll.d/airscan
install -s -D -t $(DESTDIR)$(PREFIX)$(LIBDIR)/sane $(BACKEND)
mkdir -p $(DESTDIR)$(PREFIX)/$(MANDIR)/man5
install -m 644 -D -t $(DESTDIR)$(PREFIX)$(MANDIR)/man1 $(MAN_DISCOVER)
install -m 644 -D -t $(DESTDIR)$(PREFIX)$(MANDIR)/man5 $(MAN_BACKEND)
[ "$(COMPRESS)" = "" ] || $(COMPRESS) -f $(DESTDIR)$(PREFIX)$(MANDIR)/man1/$(MAN_DISCOVER)
[ "$(COMPRESS)" = "" ] || $(COMPRESS) -f $(DESTDIR)$(PREFIX)$(MANDIR)/man5/$(MAN_BACKEND)
clean:
rm -f test $(BACKEND) tags
rm -rf $(OBJDIR)
man: $(MAN_DISCOVER) $(MAN_BACKEND)
$(MAN_DISCOVER): $(MAN_DISCOVER).md
ronn --roff --manual=$(MAN_DISCOVER_TITLE) $(MAN_DISCOVER).md
$(MAN_BACKEND): $(MAN_BACKEND).md
ronn --roff --manual=$(MAN_BACKEND_TITLE) $(MAN_BACKEND).md
test: $(BACKEND) test.c
$(CC) -o test test.c $(BACKEND) -Wl,-rpath . ${airscan_CFLAGS}
test-decode: test-decode.c $(LIBAIRSCAN)
$(CC) -o test-decode test-decode.c $(CPPFLAGS) $(airscan_CFLAGS) $(LIBAIRSCAN) $(airscan_LIBS)
I tried generating recipe using devtool but not success with it. Can anybody help me write a recipe for this one. Thanks in advance
I'm the sane-airscan author :-), but I don't know anything about yocto. So, what is your problem?
I have the following makefile. It works well for .f and .c files but when I have .f90 file and want to compile it with ifort does not work?
Could you please advise me where I should change and how?
Thanks you
FCOMPFLAGS = -O -ffixed-line-length-132
CCOMPFLAGS = -O
FFLAGS = $(FCOMPFLAGS) -fsecond-underscore
CFLAGS = $(CCOMPFLAGS)
LDFLAGS = $(FCOMPFLAGS)
LD = gfortran
FC = gfortran
MAKEFILE = Makefile
PROGRAM1 = f1
OBJS = f1.o \
f2.o \
f3.o
all: $(PROGRAM1)
$(PROGRAM1): $(OBJS) $(MAKEFILE)
$(LD) $(LDFLAGS) $(OBJS) -o $(PROGRAM1)
clean: #rm -f $(OBJS) core
when I execute "make" I get the following error,
make: *** No rule to make target `f1.o', needed by `f90_simple'. Stop.
It seems that My makefile does not recognize *.f90 files, and my other question is do we have flag for ifrot compiler to be used in makefile
Thanks
You need to add the implicit rule:
%.o : %.f90
<tab>$(FC) $(FCOMPLAGS) -c $<
I am trying to analyze the following makefile and reproduce its "behavior" step by step.
Although I type "make all" it seems this makefile skips the "all:" line and jumps straight to "build/*.o" (hence the echo's).
The file and its corresponding output:
TOOLCHAIN ?= arm-none-eabi-
SOURCES = Demo/main.c \
Demo/startup.c \
Demo/Drivers/rpi_gpio.c \
Demo/Drivers/rpi_irq.c \
Source/tasks.c \
Source/list.c \
Source/portable/GCC/RaspberryPi/port.c \
Source/portable/GCC/RaspberryPi/portisr.c \
Source/portable/MemMang/heap_4.c
OBJECTS = $(patsubst %.c,build/%.o,$(SOURCES))
INCDIRS = Source/include Source/portable/GCC/RaspberryPi \
Demo/Drivers Demo/
CFLAGS = -Wall $(addprefix -I ,$(INCDIRS))
CFLAGS += -D RPI2
CFLAGS += -march=armv7-a -mtune=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4
ASFLAGS += -march=armv7-a -mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard
LDFLAGS =
.PHONY: all clean
all: $(MOD_NAME)
echo "in all"
$(MOD_NAME): $(OBJECTS)
echo "in mod name"
ld -shared $(LDFLAGS) $< -o $#
build/%.o: %.c
echo -e "\nin build/*.o:*.c\n"
mkdir -p $(dir $#)
$(TOOLCHAIN)gcc -c $(CFLAGS) $< -o $#
build/%.o: %.s
echo -e "in build/*.o:*.s\n"
mkdir -p $(dir $#)
$(TOOLCHAIN)as $(ASFLAGS) $< -o $#
all: kernel7.list kernel7.img kernel7.syms kernel7.hex
echo -e"in kernel all\n"
$(TOOLCHAIN)size kernel7.elf
kernel7.img: kernel7.elf
$(TOOLCHAIN)objcopy kernel7.elf -O binary $#
echo -e "in kernel7.img\n"
kernel7.list: kernel7.elf
echo -e "kernel7.list\n"
$(TOOLCHAIN)objdump -D -S kernel7.elf > $#
kernel7.syms: kernel7.elf
echo -e "kernel7.syms\n"
$(TOOLCHAIN)objdump -t kernel7.elf > $#
kernel7.hex : kernel7.elf
echo -e "kernel7.hex\n"
$(TOOLCHAIN)objcopy kernel7.elf -O ihex $#
kernel7.elf: $(OBJECTS)
echo -e "kernel7.elf\n"
$(TOOLCHAIN)ld $^ -static -Map kernel7.map -o $# -T Demo/raspberrypi.ld
clean:
rm -f $(OBJECTS)
rm -f kernel7.list kernel7.img kernel7.syms
rm -f kernel7.elf kernel7.hex kernel7.map
rm -rf build
echo -e "cleaning \n"
I tried to replicate this behaviour myself with a tiny piece of code. But it doesn't seem to work:
SOURCES = Demo/Drivers/rpi_irq.c \
Demo/Drivers/rpi_gpio.c
OBJECTS = $(patsubst %.c,build/%.o,$(SOURCES))
.PHONY: all clean
all: $(MOD_NAME)
echo "making all"$(SOURCES)
$(MOD_NAME): $(OBJECTS)
echo "MOD_NAME"
build/%.o:%.c
mkdir -p $(dir $#)
arm-none-eabi-gcc -march=armv7-a -mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=har $< -o $#
As you can see thanks to the echo's my code just doesn't even build my source code. I'd expect it to go from all->MOD_NAME->build. (This is all the output I get)
So my questions are:
How does the makefile I am analyzing manage to go straight to build/*.o?
Why does my implementation, which I think should do the same doesn't even compile my source code?
The Makefile that you copied contains 2 rules for "all".
The first depends on $(MOD_NAME) which might be empty.
The second rule depends on multiple files "kernel7.*" which themselves depend on "kernel7.elf".
Finally "kernel7.elf" depends on $(OBJECTS).
This last rule is responsible that all your source files will be compiled.
The first rule with $(MOD_NAME) does not need to cause any compilation at all.
In your own Makefile you only have a rule for "all" depending on $(MOD_NAME).
If $(MOD_NAME) is empty in your Makefile as well, you do not have any dependency for "all" at all.
If "all" does not depend on anything, no source files will be compiled.
To solve your problem you need to provide some content for $(MOD_NAME).
all is trying to build $(MOD_NAME), which has dependencies of $(OBJECTS), which it is trying to build.
There are two all's here, which is a problem.
i have this makefile:
SHELL=/bin/bash
COMPILER_VERSION = "Intel 64 Compiler 16.0.0.109 Build 20150815"
SOURCES = \
ron1.f \
ron2.f \
ron3.f \
ron4.f
OBJECTS = $(SOURCES:.f=.o)
TARGET = mylib.a
FC = gfortran
FFLAGS = -O3
linux: $(TARGET)
#echo
#echo " " \
ar r $(TARGET) $(OBJECTS)
#echo
#echo " " \
ranlib $(TARGET)
#echo
$(TARGET): $(OBJECTS)
$(OBJECTS):$(SOURCES)
cleanall:
#echo
rm -f $(OBJECTS) $(TARGET)
#echo
clean:
#echo
rm -f $(OBJECTS)
#echo
.f.o:
#echo " " \
$(FC) -c $(FFLAGS) $*.f
It results the below output:
prompt> make cleanall
rm -f ron1.o ron2.o ron3.o ron4.o mylib.a
prompt> make
gfortran -c -O3 ron1.f
gfortran -c -O3 ron2.f
gfortran -c -O3 ron3.f
gfortran -c -O3 ron4.f
ar r mylib.a ron1.o ron2.o ron3.o ron4.o
ranlib mylib.a
prompt>
what i am looking to do is create a space between "prompt> make" and the first happening of gfortran.
and ideally i would like the output on the screen to first print out the contents of my COMPILER_VERSION variable before the first gfortran happens, such that the output would look like
prompt> make
makefile written for: Intel 64 Compiler 16.0.0.109 Build 20150815
gfortran -c -O3 ron1.f
gfortran -c -O3 ron2.f
gfortran -c -O3 ron3.f
and so on...
any help much appreciated.
You should add to the 'linux' target some prerequisite like 'ECHO' here:
linux: ECHO $(TARGET)
ar r $(TARGET) $(OBJECTS)
#echo
#echo " " \
ranlib $(TARGET)
#echo
ECHO:
#echo "\n\n\n\n Makefile written for the compiler version ${COMPILER_VERSION}"
thanks a bunch, that worked.
your
linux: ECHO $(TARGET)
worked great, only thing i did different than what you typed was this syntax for ECHO: which i placed at the bottom of the makefile. It allowed me to space out the screen output exactly how i wanted it.
ECHO:
#echo
#echo "Makefile written for compiler version ${COMPILER_VERSION}"
#echo
You can use echo with flag -e
#echo -e "\n"
To compile two files i have created a makefile where i use to mention the object name or i can use the pattern rule using patsubst.
# ----------------------------------------------------------------------------
# Makefile for building tapp
#
# Copyright 2010 FriendlyARM (http://www.arm9.net/)
#
ifndef DESTDIR
DESTDIR ?= /opt/FriendlyARM/tiny6410/linux/rootfs_qtopia_qt4
endif
#CFLAGS = -c -Wall -O2 # wall is for warning show and 02 is optiminisation level 2
CFLAGS = -c -O2 # wall is for warning show and 02 is optiminisation level 2
#CC = arm-linux-gcc # compiler name
CC = gcc # compiler name
LD = ld
INSTALL = install #
TARGET = led_player_project
#OBJ = led-player_backup.o led-player.o
OBJ := $(patsubst %.c,%.o,$(wildcard *.c */*.c))
#OBJ = $(shell find . -name '*.c')
all: $(TARGET)
#all: $(OBJ)
led_player_project : $(OBJ)
$(LD) $(LDFLAGS) -o $# $(OBJ) $(LIBS)
# $(LD) $(LDFLAGS) -o $# $< $(LIBS)
%.o : %.c
$(CC) $(CFLAGS) $< -o $#
#$< -o $#
install: $(TARGET)
$(INSTALL) $^ $(DESTDIR)/usr/bin
clean :
rm -rf *.o $(TARGET) $(OBJ)
# ----------------------------------------------------------------------------
.PHONY: $(PHONY) install clean
# End of file
# vim: syntax=make
#EOF
Now if my project contains folder contains subfolders & they contains further files. Then can i write pattern rule to compile every file & create an common executable?
1> Do i will have to create makefile in every-subfolder so that i can invoke that makefile from main makefile, like integrating static driver to linux kernel each driver have respective makefile ?
2> Or common makefile for full project ?
3> can i use patsubst to compile every file without mentioning there name.
4> How can i combine every *.o to create on executable called main.
Edit :---
#Jan Hudec
I have modified my makefile as per your comment (i have posted it above). Now i am just trying with two folders inside my main folder. I am getting following error
Folder structure :--
main Folder ----> one Folder
----> two Folder
Folder Main contains :--
main.c
main.h
Makefile
Folder one contains :--
one.c
one.h
Folder two contains :--
two.c
two.h
main.c content :--
#include <stdio.h>
#include <stdlib.h>
#include "main.h"
int main()
{
char *p;
printf("\n\n main \n");
one();
two();
return 0;
}
main.h content :---
#include "one/one.h"
#include "two/two.h"
one.c content :---
#include <stdio.h>
#include <stdlib.h>
#include "one.h"
void one()
{
printf("\n one \n");
}
one.h content :---
void one();
two.c content :---
#include <stdio.h>
#include <stdlib.h>
#include "two.h"
void two()
{
printf("\n two \n");
}
two.h content :---
void two();
Error i got at make time :----
ignite#ignite:~/testing/main$ make
gcc -c -O2 main.c -o main.o
gcc -c -O2 one/one.c -o one/one.o
gcc -c -O2 two/two.c -o two/two.o
ld -o led_player_project main.o one/one.o two/two.o
ld: warning: cannot find entry symbol _start; defaulting to 0000000008048080
main.o: In function `main':
main.c:(.text.startup+0x11): undefined reference to `puts'
one/one.o: In function `one':
one.c:(.text+0xb): undefined reference to `puts'
two/two.o: In function `two':
two.c:(.text+0xb): undefined reference to `puts'
make: *** [led_player_project] Error 1
ignite#ignite:~/testing/main$
Ad 1 and 2: The filenames can safely include directories and % matches / as necessary. So you can easily have:
$(wildcard subdir/*.c) $(wildcard anotherdir/*.c)
or even
$(wildcard */*.c)
... or as suggested by keltar in comment
$(shell find . -name '*.c')
which is recursive.
Ad 3: You are doing it.
Ad 4: Create a target with $(OBJ) as dependencies and use the automatic variable just as you do for compilation:
main : $(OBJ)
$(LD) $(LDFLAGS) -o $# $< $(LIBS)
Perhaps another solution too. I have a source directory in my project dir which contains subdirectories. And I dont want have a Makefile in every subdirectories or something else. And I want to build everything only with one makefile in rootdir of project: So for my static library in c++ i did this makefile. Perhaps it could be a solution for you too. But I didnt test it well with paralell builds via "make -j4" or so.
BUILDCXX=g++-10
CHECKCXX=clang++-12
CXXFLAGS=-std=c++17 -Wall -Werror -Wextra -g -pg -O0 -I. -DDEBUG
CXXFLREL=-std=c++17 -Wall -Werror -Wextra -O3 -s -I. -DNDEBUG
CXXFLAGSLIB=$(CXXFLAGS)
CXXFLAGSTST=$(CXXFLAGS) -DRLOG_COMPONENT="clbc"
LDFLAGS=
LDFLAGSLIB=$(LDFLAGS)
LDFLAGSTST=$(LDFLAGS) -L./target/lib -lUnitTest++ -lclbc
OUTDIR=target
OUTDIRLIB=$(OUTDIR)/lib
OUTDIRTST=$(OUTDIR)/bin
OUTDIROBJ=$(OUTDIR)/obj
OUTFILELIB=libclbc.a
OUTFILETST=runtests
SRCDIR=source
SRCDIRLIB=$(SRCDIR)/lib
SRCDIRTST=$(SRCDIR)/test
SRCDIRSLIBR := $(shell find $(SRCDIRLIB) -maxdepth 3 -type d)
SRCFILESLIB := $(foreach dir,$(SRCDIRSLIBR),$(wildcard $(dir)/*.cpp))
OBJFILESLIB := $(addprefix $(OUTDIROBJ)/,$(notdir $(patsubst %.cpp,%.o,$(SRCFILESLIB))))
SRCDIRSTSTR := $(shell find $(SRCDIRTST) -maxdepth 3 -type d)
SRCFILESTST := $(foreach dir,$(SRCDIRSTSTR),$(wildcard $(dir)/*.cpp))
OBJFILESTST := $(addprefix $(OUTDIROBJ)/,$(notdir $(patsubst %.cpp,%.o,$(SRCFILESTST))))
.PHONY: all
all: clean lib
check-syntax:
$(CHECKCXX) $(CXXFLAGS) -s -o /dev/null -S $(CHK_SOURCES)
clean:
#rm -rf $(OUTDIR)
lib:$(OBJFILESLIB)
#mkdir -p $(OUTDIRLIB)
#echo " TargetLib :" $(OUTDIRLIB)/$(OUTFILELIB)
# ar rcs $(OUTDIRLIB)/$(OUTFILELIB) $^
test:$(OBJFILESTST)
#mkdir -p $(OUTDIRTST)
#echo "TargetTest :" $(OUTDIRTST)/$(OUTFILETST)
# $(BUILDCXX) $(OBJFILESTST) -o $(OUTDIRTST)/$(OUTFILETST) $(LDFLAGSTST)
release: CXXFLAGSLIB=$(CXXFLREL)
release:$(OBJFILESLIB)
#mkdir -p $(OUTDIRLIB)
#echo "RTargetLib :" $(OUTDIRLIB)/$(OUTFILELIB)
# ar rcs $(OUTDIRLIB)/$(OUTFILELIB) $^
define set_real_src_file
$(eval REAL_SRC_FILE=$(strip $(1)))
endef
define set_nothing
endef
define get_real_src_file
$(if $(strip $(findstring $(strip $(1)),$(strip $(2)))),$(call set_real_src_file,$(2)),$(call set_nothing))
endef
define get_source_file
#echo ObjectFile : $(1)
$(eval REAL_SRC_SEARCH=$(notdir $(patsubst %.o,%.cpp,$(1))))
$(eval REAL_SRC_FILE=)
$(foreach word,$(2), $(call get_real_src_file, $(REAL_SRC_SEARCH),$(word)))
endef
$(OBJFILESLIB): $(SRCFILESLIB)
#mkdir -p $(OUTDIROBJ)
$(call get_source_file,$#,$^,$<)
# $(BUILDCXX) $(CXXFLAGSLIB) -c $(REAL_SRC_FILE) -o $#
$(OBJFILESTST): $(SRCFILESTST)
#mkdir -p $(OUTDIROBJ)
$(call get_source_file,$#,$^,$<)
# $(BUILDCXX) $(CXXFLAGSTST) -c $(REAL_SRC_FILE) -o $#
But I guess it runs only with GNUMake and no other implementations of make.