What is the significance order of this Verilog initialization syntax? - verilog

Question

This is a simple SystemVerilog question that I am having a surprisingly difficult time finding the answer for.
In this kind of bit array initialization syntax, is the b[0] part assigned to a's most significant bit, or the least significant bit?
bit a[7:0];
bit b[7:0] = 8'hff;
bit c[7:0] = 8'h00;
a = {b[0], c[6:0]};
So does a[0] == 1 or a[7] == 1?

Answer 1

The reason you've found it hard to find an answer is because the result is dependent on how you've declared things.
You've declared a to be [7:0]. Therefore the bits in a are arranged like this:
a7 a6 a5 a4 a3 a2 a1 a0
You then assign {b[0], c[6:0} to a:
a7 a6 a5 a4 a3 a2 a1 a0 = b0 c6 c5 c4 c3 c2 c1 c0
1 0 0 0 0 0 0 0 = 1 0 0 0 0 0 0 0
A[7] == 1
If you'd declared a to be [0:7] the result would have been:
a0 a1 a2 a3 a4 a5 a6 a7 = b0 c6 c5 c4 c3 c2 c1 c0
1 0 0 0 0 0 0 0 = 1 0 0 0 0 0 0 0
A[0] == 1

Answer 2

b[0] is assigned to the most significant bit, a[7]; i.e. a[7] == 1.

Answer 3

However, I'm not sure it's typo or your intention to use unpacked declaration. bit a[7:0] is an unpacked array, it does not mean continuous storage and it can not be directly assigned packed or integral value.
Following is adopted from SystemVerilog for Design, P.114, 5.3.1 Unpacked arrays
Unpacked array stores each element independently, but grouped under a common array name.
P.122, 5.3.5 Assigning values to arrays
SystemVerilog extends Verilog with two additional ways to assign values to unpacked arrays:
- The entire array can be assigned a list of values
- A slice of the array can be assigned a list of values.
The list of values is specified between '{ } braces, the same as with initializing unpacked arrays.
For packed array, bit [7:0] a, we do have correct answer from Paul.