I am new to programming in general and I find myself depending too much on conditional statements. I find them similar to my train of thought when coding which makes them easy to implement.
Below I have a small code snippet in Verilog which controls a digital clock display. The entire code is pretty much laid out in this way. The code works and is pretty readable. However, I find it to be inelegant. Is it possible to simplify the code while at the same time improving readability?
if (cnt >= clkspeed) begin
cnt = 0;
out0 <= out0 + 4'h1;
// LED0 > 9 -> LED1 += 1
if (out0 == 4'h9) begin
out0 <= 4'h0;
out1 <= out1 + 4'h1;
// LED1 > 5 -> LED2 += 1
if (out1 == 4'h5) begin
out1 <= 4'h0;
out2 <= out2 + 4'h1;
// LED2 > 9 -> LED3 += 1
if (out2 == 4'h9) begin
out2 <= 4'h0;
out3 <= out3 + 4'h1;
// LED3 > 5 -> LED3 = 0
if (out3 == 4'h5) begin
out3 <= 4'h0;
end
end
end
end
end
Your problem here is that you perform the same operation four times, as you store your data in scalar variables. The solution for this case would be to store the numbers in an array, and loop through them. The pseudocode of this is something like:
array<int> digits;
int position = digits.length();
while (position >= 0) {
digits[position] = (digits[position] + 1) % 10;
if (digits[position]>0) break; // if there is no carry, just break
position--;
}
This code assumes that every digit counts up to 9. So you still have to add the logic for handling LED1 and LED3... (Through using another array, or if you have OOP creating a LED object which can store the actual number and the limit for the led...)
Related
I am receiving this error from Quartus when trying to compile:
Error (10200): Verilog HDL Conditional Statement error at
time_of_day_FSM.v(166): cannot match operand(s) in the condition to
the corresponding edges in the enclosing event control of the always
construct
Here is some background. I am making a clock, and for this always block, I want to increment and set certain values to resemble the behavior of a clock in the format of hh:mm:ss. I have a clock source that goes high every millisecond, and am using a counter to set the secondPassed reg.
I want the code in the block to update every time a second passes, like a clock, or KEY[2] is pressed on my board (down = 0), as this is what the user uses to increment the hours, minutes, or seconds when setting the clock time. Here is the always block in question (sorry for the nested if statements, I can't think of a better way to do it):
// every second. Used just to keep time going. Independent of states.
always #(posedge secondPassed, negedge KEY[2], negedge KEY[0]) begin
if(KEY[0] == 0) begin
hr1 <= 1;
hr0 <= 2;
min1 <= 0;
min0 <= 0;
sec1 <= 0;
sec0 <= 0;
end
else if(secondPassed == 1 || KEY[2] == 0) begin // I don't care about explicitly stating the conditions, as the sensitivity list covers that right?
if(sec0 == 9) begin
sec0 <= 0;
if(sec1 == 5) begin
sec1 <= 0;
if(min0 == 9) begin
min0 <= 0;
if(min1 == 5) begin
min1 <= 0;
if(hr1 == 1) begin
if(hr0 == 2) begin
hr0 <= 1; // go to 1 o'clock
hr1 <= 0;
end
else hr0 <= hr0 + 1;
end
else hr0 <= hr0 + 1;
end
else min1 <= min1 + 1;
end
else min0 <= min0 + 1;
end
else sec1 <= sec1 + 1;
end
else begin
sec0 <= sec0 + 1;
end
just_flashed <= ~just_flashed;
end // end big else
end // end always
My question is: Why does the Quartus compiler complain if I try to make the non-reset scenario JUST AND ELSE, like this:
// every second. Used just to keep time going. Independent of states.
always #(posedge secondPassed, negedge KEY[2], negedge KEY[0]) begin
if(KEY[0] == 0) begin
hr1 <= 1;
hr0 <= 2;
min1 <= 0;
min0 <= 0;
sec1 <= 0;
sec0 <= 0;
end
else begin // this is causing the issue. compiler complains .
// same logic to drive clock as above
just_flashed <= ~just_flashed;
end // end big else
end // end always
I feel I have seen many examples where people simply use and else begin end for their code. My code seems to want my to EXPLICITLY restate the conditions of the sensitivity list for the else if. Any explanation? I am new to large verilog projects.
You are mixing combinational logic and synchronous logic in the always block and this is bad habit of coding. Generally, there are 2 main always blocks in most designs.
A combinational:
always#(*) // * adds anything under this always block to sensitivity list.
begin // Which makes this always block combinational.
count_reg_d <= somelogic;
end
Then these combinational logic is assigned to proper registers in the sequental
always block:
always#(posedge clk, negedge rst)
begin
if(~rst)
count_reg_q <= 0;
else
begin
count_reg_q <= count_reg_d;
end
end
By coding this way you avoid mixed always blocks, and the code is much more readable and closer to hardware that is being synthesized. So if you update the always blocks' sensitivity list properly the problems has to be solved.
I have written up/down counter and created code for settable starting point. So far so good but I can't think of how to add it to the counter. I have to highlight that I'm completely new to Verilog and similar languages.
//UTILS
reg [2:0] delay;
wire clock;
reg[3:0] tens;
reg[3:0] units;
wire[5:0] number;
reg[13:0] shift;
integer i;
//ASSIGNS
assign number[5:0] = SW[5:0];
assign up = SW[7];
assign start = SW[6];
//PRESCALER
always# (posedge MCLK)
begin
delay <= delay + 1;
end
assign clock = &delay;
//MAIN COUNTER
always# (posedge clock)
begin
if (start)
begin
if (up) //going up
begin
if (units == 4'd3 && tens == 4'd6)
begin //63 reached
units <= 0;
tens <=0;
end
if (units==4'd9)
begin //x9 reached
units <= 0;
tens <= tens + 1;
end
else
units <= units + 1; //typical case
end
else //goin down
begin
if (units == 4'd0)
if ( tens ==4'd0) //00 reached back to 63
begin
units <= 4'd3;
tens <= 4'd6;
end
else
begin //x0 reached
tens <= tens-1;
units <= 4'd9;
end
else
begin //typical case
units <= units -1;
end
end
end
end //MAIN COUNTER END
Here I don't know how to merge this two pieces, I would love to have it like this
if start
always# posedge clock
/counting/
else
/* change number nearly functionally(immediately when change occurs)*/
Adding it into if(start) else seems to do the work but only on positive edge of quite low frequency clock. As far as I know i can't use one reg in two different ALWAYS#.
/* // Clear previous number and store new number in shift register
shift[13:6] = 0;
shift[5:0] = number;
//BINARY TO BCD
for (i=0; i<6; i=i+1)
begin
if (shift[9:6] >= 5)
shift[9:6] = shift[9:6] + 3;
if (shift[13:10] >= 5)
shift[13:10] = shift[13:10] + 3;
shift = shift << 1;
end
units <= shift[9:6];
tens <= shift[13:10];
*/
dek7seg Is 7-segment display which is 100% fine (professor's code).
dek7seg ss1(
.bits(units[3:0]),
.seg(DISP1[6:0])
);
dek7seg ss10(
.bits(tens[3:0]),
.seg(DISP2[6:0])
);
endmodule
You are using a derived clock to control your MAIN COUNTER. Instead use the main clock MCLK and use the logic for delay as a conditional statement.
Since you want store an new values on the change of number, then you will need to store the the previous number value and compare.
Based on your description, your code should look something like this:
//MAIN COUNTER
always# (posedge MCLK)
begin
if (start && &delay)
begin
/* your up/down logic here */
end
else if (number != prev_number)
begin // Clear previous number and store new number
prev_number <= number;
units <= new_units;
tens <= new_tens;
end
end
// Calculate new units and tens from number
always #* begin
shift[13:6] = 0;
shift[5:0] = number;
//BINARY TO BCD
for (i=0; i<6; i=i+1) begin
if (shift[9:6] >= 5)
shift[9:6] = shift[9:6] + 3;
if (shift[13:10] >= 5)
shift[13:10] = shift[13:10] + 3;
shift = shift << 1;
end
new_units = shift[9:6];
new_tens = shift[13:10];
end
I'm trying to build a task, which must delve into some hierarchy, that can concisely compare different pins on a particular instance. In particular, I'd like to do something like the following:
task check_expected;
input integer pin;
input [9:0] expected;
integer i, j;
reg [9:0] check;
begin
j = 0;
for (i = 0; i < 20; i = i + 1) begin
case (pin)
0: begin
check[0] = test.inst[i].lane_0.PIN_FIRST;
check[1] = test.inst[i].lane_1.PIN_FIRST;
...
check[9] = test.inst[i].lane_9.PIN_FIRST;
end
1: begin
check[0] = test.inst[i].lane_0.PIN_SECOND;
check[1] = test.inst[i].lane_1.PIN_SECOND;
...
check[9] = test.inst[i].lane_9.PIN_SECOND;
end
...
9: begin
check[0] = test.inst[i].lane_0.PIN_TENTH;
check[1] = test.inst[i].lane_1.PIN_TENTH;
...
check[9] = test.inst[i].lane_9.PIN_TENTH;
end
endcase
if (check[0] !== expected[j*10 + 0]) begin
TEST_FAILED = TEST_FAILED + 1;
$display("ERROR Expected=%b, # %0t",expected[j*10 + 0],$time);
end
if (check[1] !== expected[j*10 + 1]) begin
TEST_FAILED = TEST_FAILED + 1;
$display("ERROR Expected=%b, # %0t",expected[j*10 + 1],$time);
end
...
if (check[9] !== expected[j*10 + 9]) begin
TEST_FAILED = TEST_FAILED + 1;
$display("ERROR Expected=%b, # %0t",expected[j*10 + 9],$time);
end
end
end
endtask
Unfortunately, attempting to do the above throws a NOTPAR error during elaboration, claiming that it is unacceptable to assign a register to a non-constant (it doesn't like any lines like check[0] = test.inst[i].lane_0.PIN_FIRST;). This is just for testing purposes, not anything synthesizeable, by the way.
Can someone explain why this is disallowed and suggest a different solution? It's looking like I'll need to write a task for each and every loop iteration, and that seems like it would be needlessly bloated and ugly.
Thanks
To answer my own question, the answer is that there is no way to do it with Verilog. Verilog is an incredibly dumb (in terms of capabilities) language, and, with a task, can only support constant indices for module instances. No looping is possible.
My project is to design a verilog code that gives an output on the 7segments (HEX0,HEX1,HEX2,HEX3) and output must increase when the button KEY0 is pressed on the board 1 by 1, and decrease when the button KEY1 is pressed using Altera Board (Cyclone II-EP2C35F672).
I achieve to increase 1 by 1 but when I try to decrease with the same logic, I take irrelevant outputs. Is it possible to give me a way solving the problem.
My verilog code is that:
module sevensegment (KEY,HEX0,HEX1,HEX2,HEX3);
input [3:0]KEY;
output [0:6]HEX0;
output [0:6]HEX1;
output [0:6]HEX2;
output [0:6]HEX3;
counter D1(~KEY,HEX0,HEX1,HEX2,HEX3);
endmodule
module counter(in,out,out1,out2,out3);
input [3:0]in;
output [6:0]out;
output [6:0]out1;
output [6:0]out2;
output [6:0]out3;
reg[15:0] tmp;
always #(posedge in)
begin
if(~in[0])
begin
tmp <= tmp + 1'b1;
end
else if(~in[1])
begin
tmp <= tmp - 1'b1;
end
end
displaysevensegment first_digit(tmp[3:0],out);
displaysevensegment second_digit(tmp[7:4],out1);
displaysevensegment third_digit(tmp[11:8],out2);
displaysevensegment fourth_digit(tmp[15:12],out3);
endmodule
module displaysevensegment(in,out);
// abcdefg
parameter BLANK = 7'b1111111;
parameter ZERO = 7'b0000001;
parameter ONE = 7'b1001111;
parameter TWO = 7'b0010010;
parameter THREE = 7'b0000110;
parameter FOUR = 7'b1001100;
parameter FIVE = 7'b0100100;
parameter SIX = 7'b0100000;
parameter SEVEN = 7'b0001111;
parameter EIGHT = 7'b0000000;
parameter NINE = 7'b0000100;
parameter TEN = 7'b0001000;
parameter ELEVEN = 7'b1100000;
parameter TWELVE = 7'b0110001;
parameter THIRTEEN = 7'b1000010;
parameter FOURTEEN = 7'b0110000;
parameter FIFTEEN = 7'b0111000;
input [3:0]in;
output [6:0]out;
assign out = (in == 0) ? ZERO:
(in == 1) ? ONE:
(in == 2) ? TWO:
(in == 3) ? THREE:
(in == 4) ? FOUR:
(in == 5) ? FIVE:
(in == 6) ? SIX:
(in == 7) ? SEVEN:
(in == 8) ? EIGHT:
(in == 9) ? NINE:
(in == 10) ? TEN:
(in == 11) ? ELEVEN:
(in == 12) ? TWELVE:
(in == 13) ? THIRTEEN:
(in == 14) ? FOURTEEN:
(in == 15) ? FIFTEEN:BLANK;
endmodule
The simulate will not recognize the raising edge of in[1] when the sensitivity list is describes as posedge in. Only the LSB will be monitored. Instead use a bitwise operation to detect when a key is pressed and use this as the clocking signal.
wire gen_clk = |in; // bitwise OR
always #(posedge gen_clk) begin
if (in[0]) tmp <= tmp + 1'b1;
else if (in[1) tmp <= tmp - 1'b1;
end
wire gen_clk = ∈ // bitwise AND
always #(posedge gen_clk) begin
if (in[0]) tmp <= tmp + 1'b1;
else if (in[1) tmp <= tmp - 1'b1;
end
Side note: Deep nested muxes often result in lower performance more area then a case statement. This is because most synthesizer will not optimize inline muxes (?:). Recommend re-coding displaysevensegment with a case statement like:
input [3:0] in;
output [6:0] out;
reg [6:0] out; // out needs to be a reg
always #* begin
case(in)
4'h0 : out = ZERO;
4'h1 : out = ONE;
// ...
4'hE : out = FOURTEEN;
4'hF : out = FIFTEEN;
default: out = BLANK;
endcase
end
I am coding in Verilog a typical count-to-n-then-reset-to-0 counter. My module has the logic to increment and reset the counter.
My issue is that I don't know where the counter itself should be defined.
I could pass the counter (as inout?) to the module. That's ok, but the counter still has to be defined somewhere so it this doesn't do me any good.
Nothing else except this module should touch the counter, so I'd like to have the counter created within this module, and not passed in or out.
Is this reasonably standard, and if so, will someone point to a reference please on how to instantiate the counter?
(I'm on day 2 of Verilog, so be afraid, heh)
EDIT - here's the code. As far as I can tell, it works. I haven't implemented DIR == REVERSE yet.
Couple of interesting gotchas. The (now commented out) STEPPER=0 line was causing an error in a schematic; it thought that STEPPER was tied to ground as well as other logic.
Also, I use = instead of <= in some places involving counter - I was getting timing problems (I suppose.) The procedural assignment removed (hid?) the problem.
module cam(
input [7:0] DIVISOR,
input DIR,
input SPINDLE,
output reg STEPPER
);
parameter FORWARD = 1'b1;
parameter REVERSE = !FORWARD;
reg[7:0] counter = 0;
always #(posedge SPINDLE) begin
// STEPPER = 0;
if (DIR == FORWARD) begin
counter = counter + 1;
if (counter == DIVISOR) counter = 0;
end
else begin
// counter <= counter - 1;
// if (counter == (-1)) counter <= DIVISOR;
end
end
always #(negedge SPINDLE) begin
STEPPER = (counter == 0) ? 1 : 0;
end
endmodule
Should just be defined as a register within the module. Here's an example from some of my code.
module trigger(clk, rxReady, rxData, txBusy, txStart, txData);
input clk;
input [7:0] rxData;
input rxReady;
input txBusy;
output reg txStart;
output reg[7:0] txData;
integer count81; // Number of cells received over serial (start solving after 81)
reg[8:0] data[0:8][0:8];
integer state;
always #(posedge clk) begin
case (state)
read:
if (rxReady) begin
data[count81 % 9][count81 / 9] = rxData ? 1<<(rxData-1) : -1;
if (count81 < 80) count81 <= count81 + 1;
else begin
count81 <= 0;
state <= solving;
end
end
etc....
endcase
end
endmodule
Congrats on getting out of the Java world for the time being. FPGAs are the only thing that seems exciting anymore.