Good day,
I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well.
Is there a way to reset the contents back to zero without power-cycling/reflashing/etc the FPGA? There seems to be no such option in the megawizard plugin manager, and I would like to avoid wasting a bunch of logic which just goes and sequentially writes zero to every address...
I have looked around and there is no reference to such a mechanism, but I thought I'd ask just in case someone knew a handy trick :] By the way I'm working in VHDL but I should be able to translate any Verilog.
Datasheet (does not contain the answer!) : http://www.altera.com/literature/hb/stx3/stx3_siii51004.pdf
Thanks in advance,
- Thomas
PS: This be my first post here, so if I've violated any etiquette please let me know :)
Sorry, the conventional ways to do that are:
to re-configure the fpga (you could trigger that from within your hardware if you don;t mind the whole thing "disappearing" while it reconfigures)
explicitly write zeros in (as you already suggested)
At the wackier end of the solution space, I guess you could also wire something up to the JTAG port if you already have a microcontroller either in the FPGA or outside - you might be able to overwrite the RAM contents that way too.
Related
I've been trying to find a way to capture keyboard input during runtime simulation of my Verilog code. Is this even possible?
I have taken a look at resources like asic-world and the Quick Reference for Verilog found on Google, but found nothing regarding a way to take keyboard inputs.
There seems to be a fundamental misunderstanding here in the difference between a hardware description language used to simulate a design versus using that same description to implement a design in actual hardware. It's like drawing a picture of a pinwheel, blowing on that picture, and expecting the pinwheel to start turning.
You can certainly build a 3-D model of that pinwheel, simulate the force of the wind on that model and watch it turn, and then send that model to a 3-d printer to get your pinwheel. I suppose you could put wind sensors in front of your monitor, and write a program that converts a value from the sensor to a value used in the simulation. The point is, the simulator has no knowledge that the value came from someone blowing on the monitor, it just sees a parameter value change.
Unless you are designing the keyboard hardware yourself and simulating that, there really is not much point in taking keyboard input from a computer and using that to stimulate your design in simulation. The operating system has already abstracted away the keyboard hardware and provides you with a string of character codes. The reason you are simulating in the first place is to verify the functionality of your design. If you find a problem, you are going to want to replay the exact same stimulus until you fix your problem.
Just like the pinwheel example, I do know it's possible for someone to set up a program that reads keyboard input and provides that as stimulus to a simulation. But that involves inter-process communication(IPC) and specific tool knowledge to set that up.
I'm trying to create a Nintendo Switch Emulator and I am connecting instructions to the operations from assembly code for the ARM57 chips that make up the Tegra X1. I have found this following data sheet:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0488c/DDI0488C_cortex_a57_mpcore_r1p0_trm.pdf
but unfortunately it is very vague and hard to understand, but I wanted to know what does the "Reserved" section mean? Has it got something to do with how it holds the registers. It can be found at page. 453. The Reserved operation is called quite often. If someone can find a better datasheet that would be great too although I must know, what is the "Reserved" Operation.
Generally speaking, this refers to bits in a register that currently don't do anything, but might in a future version of the hardware. The programmer is being warned not to accidentally change their values when manipulating other bits in the register. When writing an emulator, you should ignore these bits completely.
by jasonharper
I'm in the process of updating an old BS2 (basic stamp) Rev for an Ardunio for a piece of hardware for the company I work for, and I've just encountered a couple pieces of code that I'm not too sure on and I'd like some clarification. I've looked for a bit, but a couple of these are just not listed anywhere. I can't post the full code here for obvious reason, so I'll clarify other information as needed.
CONVERT_AD:
CONFIG_AD = CONFIG_AD |%1011 'Set all bits except channel.
LOW CHIP_SELECT 'Activate the ADC.
SHIFTOUT DATA_IO,CLOCK,LSBFIRST,[CONFIG_AD\4] 'Send config bits.
SHIFTIN DATA_IO,CLOCK,MSBPOST,[AD_RESULT\12] 'Get data bits.
HIGH CHIP_SELECT 'Deactivate the ADC.
RETURN
The line that's got me here is the CONFIG_AD = CONFIG_AD |%1011. It appears to obvious be a binary conversion, but I don't know what the operators are in this case. It looks like a 'assign'.
The value of CONFIG_AD is a word, if that's of any importance. It is hooking a pin for a half-duplex communication with a LTC1298 CN8 A-D converter. I've also read the data sheet, but it doesn't provide a lot of information regarding this. I think it's a 12 bit device? (though I'm not sure).
Just a lot of this information is really outdated and not maintained, so finding good information is really proving to be a bitch.
Also, the shift in/shift out, I'm curious why they have the two division functions on this? It seems to be converting it to another format, any explanation of why this is?
And on a slightly related note that is more of a save me time question, rather than I need to know, for the basic stamp, does anyone know it's hertz rates for the clock speed?
I'm trying to interface a Nexys3 board with a VmodTFT via a VHDCI connector. I am pretty new to FPGA design, and although I have experience with micro-controllers. I am trying to approach the whole problem as a FSM. However, I've been stuck on this for quite some time now. What signals constitute my power up sequence? When do I start sampling data? I've looked at the relevant datasheets and they don't make things very clearer. Any help would be greatly appreciated (P.S : I use Verilog for the design).
EDIT:
Sorry for the vagueness of my question. Here's specifically what I am looking at.
For starters, I am going to overlook the touch module. I want to look at the whole setup as a FSM. I am assuming the following states:
1. Setup connection or handshake signals
2. Switch on the LCD
3. Receive pixel data
4. Display video
5. Power off the LCD
Would this be a reasonable FSM? My main concerns are with interpreting the signals. Table 5 in the VmodTFT_rm manual shows a list of signals; however, I am having trouble understanding what signals are for what (This is my first time with display modules). I am going to assume everything prefixed with TFT_ is for the display and everything with TP_ is for the touch panel (Please correct me if I'm wrong). So what signals would I be changing in each state and what would act as inputs?
Now what changes should I make to accommodate the touch panel too?
I understand I am probably asking for too much, but I would greatly appreciate a push in the right direction as I am pretty stuck with this for a long time.
Your question could be filled out a little better, it's not clear exactly what's giving you trouble.
I see two relevant docs online (you may have seen these):
Schematic: https://digilentinc.com/Data/Products/VMOD-TFT/VmodTFT_sch.pdf
User Guide: https://digilentinc.com/Data/Products/VMOD-TFT/VmodTFT_rm.pdf
The user guide explains what signals are part of the Power up sequence
you must wait between 0.5ms and 100ms after driving TFT-EN before you can drive DE and the pixel bus
You must wait 0 to 200ms after setting up valid pixel data to enable the display (with DISP)
You must wait 160ms after enabling DISP before you start pulsing LED-EN (PWM controls the backlight)
Admittedly the documentation doesn't look great and some of the signals names are not consistent, but I think you can figure it out from there.
After looking at the user guide to understand what the signals do, look at the schematic to find the mapping between the signal names and the VHDCI pinout. Then when you connect the VHDCI pinout to your FPGA, look at your FPGA's manual to find mapping between pins on the VHDCI connector and balls of the FPGA, and then you can use the fpga's configuration settings to map an FPGA ball to a logical verilog input to your top module.
Hope that clears things up a bit, but please clarify your question about what you don't understand.
Imagine the radio of a car, does the electro magnetic fields through which the car goes through, have interference in the processing? It's easy to understand that a strong field can corrupt data. But what about the data under processment? Can it also be changed?
If so how could you protect your code against this? (without electrial protections just code ones)
For the most robust mission critical systems you use multiple processors and compare results. This is what we did with aircraft auto pilot (autolanding). We had three autopilots, one flying the aircraft and two check that one. If any one of the three disagreed, it was shut down.
You're referring to what Wikipedia calls soft errors. The traditional, industry-accepted work-around for this is through redundancy, as Jim C and fmsf noted.
Several years ago, our repair department's analysis showed an unacceptable number of returned units with single-bit errors in the battery-backed SRAM that held the firmware. Despite our efforts at root-cause analysis, we were unable to explain the source of the problem. At that point a hardware change was out of the question, so we needed a software-only solution to treat the symptom.
We wanted a reliable fix that we could implement simply and quickly, so we generated parity checks on blocks of code in the SRAM. We chose a block size that required very little additional storage for the parity data, yet provided enough redundancy to detect and correct any of the errors we'd seen and then some. It logs the errors it detects and indicates whether it can correct them, so we still know when bit errors occur in the field. So far, so good!
Our product manager did some additional research out of curiosity and convinced himself that the culprit was cosmic radiation. We never proved it unequivocally, but he was satisfied that the number of errors seemed to agree with what would be expected based on the data he found. I'm just glad the returns have stopped.
I doubt you can.
Code that is changed won't run, so likely your program(s) will crash if you have this problem.
This is a hardware problem.